公开(公告)号：US20050080970A1

公开(公告)日：2005-04-14

申请号：US10676890

申请日：2003-09-30

Applicant: Stalinselvaraj Jeyasingh ,  Andrew Anderson ,  Steven Bennett ,  Erik Cota-Robles ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig

Inventor： Stalinselvaraj Jeyasingh ,  Andrew Anderson ,  Steven Bennett ,  Erik Cota-Robles ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig

IPC: G06F9/455 ,  G06F9/48 ,  G06F13/24

CPC classification number: G06F13/24 ,  G06F9/45533 ,  G06F9/4812

Abstract: In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.

Abstract translation: 在一个实施例中，装置包括与中断控制器和多个中断请求线耦合的一组多路复用块以及耦合到该多路复用块集合的虚拟机监视块（VMM）。 每个复用块对应于不同的中断请求行。 每个多路复用块将根据该多路复用块的当前配置值将经由相应的中断请求线接收到的中断请求信号发送到中断控制器或VMM块。

公开(公告)号：US20050080937A1

公开(公告)日：2005-04-14

申请号：US10973678

申请日：2004-10-25

Applicant: Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Michael Kozuch ,  Gilbert Neiger ,  Richard Uhlig

Inventor： Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Michael Kozuch ,  Gilbert Neiger ,  Richard Uhlig

IPC: G06F12/10 ,  G06F3/00

CPC classification number: G06F12/1027 ,  G06F9/30076 ,  G06F12/1036 ,  G06F2212/151

Abstract: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

Abstract translation: 本发明的一个实施例是使翻译后备缓冲器（TLB）中的条目无效的技术。 处理器中的TLB具有多个TLB条目。 当执行无效操作时，每个TLB条目与虚拟机扩展（VMX）标签字相关联，指示相关联的TLB条目是否根据处理器模式而无效。 处理器模式是虚拟机（VM）中的执行之一，而不是虚拟机中的执行。 无效操作属于一个无效的无效操作集合，它由（1）可能为空的操作集合组合，使一组可变数量的TLB条目无效，（2）一组可能的空白操作，使一个TLB无效 条目，（3）使多个TLB条目无效的可能的一组操作，（4）启用和禁用虚拟存储器的使用的可能的一组可能的空操作，以及（5）配置物理的可能的一组操作 地址大小，页面大小或其他虚拟内存系统行为，以改变物理机器解释TLB条目的方式。

公开(公告)号：US06754815B1

公开(公告)日：2004-06-22

申请号：US09618659

申请日：2000-07-18

Applicant: Carl M. Ellison ,  Roger A. Golliver ,  Howard C. Herbert ,  Derrick C. Lin ,  Francis X. McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James A. Sutton ,  Shreekant S. Thakkar ,  Millind Mittal

Inventor： Carl M. Ellison ,  Roger A. Golliver ,  Howard C. Herbert ,  Derrick C. Lin ,  Francis X. McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James A. Sutton ,  Shreekant S. Thakkar ,  Millind Mittal

IPC: G06F15177

CPC classification number: G06F21/74 ,  G06F9/4401 ,  G06F21/62 ,  G06F2221/2143

Abstract: The present invention provides a method, apparatus, and system for invoking a reset process in response to a processor being individually reset. The reset processor operates within a platform in an isolated execution mode and is associated with an isolated area of memory. An initialization process is invoked for an initializing processor. The initialization process determines whether or not a cleanup flag is set. If the cleanup flag is set, the isolated area of memory is scrubbed. In one embodiment, when a last processor operating in the platform is reset, it is reset without clearing the cleanup flag. Subsequently, an initializing processor invokes the initialization process. The initialization process determines that the cleanup flag is set. The initialization process invokes the execution of a processor nub loader. If the cleanup flag is set, the processor nub loader scrubs the isolated area of memory and invokes a controlled close for the initializing processor. The controlled close clears the cleanup flag. The initializing processor then re-performs the initialization process. Upon the second iteration of the initialization process, with the cleanup flag not set, a new isolated area of memory is created for the initializing processor.

Abstract translation: 本发明提供了一种响应于处理器被单独复位来调用复位过程的方法，装置和系统。 复位处理器在孤立执行模式的平台内运行，并与存储器的隔离区域相关联。 初始化处理器调用初始化过程。 初始化过程确定是否设置清除标志。 如果清除标志置位，则清除隔离区的内存。 在一个实施例中，当在平台中操作的最后一个处理器被重置时，它被重置而不清除清除标志。 随后，初始化处理器调用初始化过程。 初始化过程确定清除标志被设置。 初始化过程调用处理器nub加载器的执行。 如果清除标志置位，则处理器nub加载器将擦除存储器的隔离区域，并为初始化处理器调用受控关闭。 受控关闭清除清除标志。 初始化处理器然后重新执行初始化过程。 在初始化过程的第二次迭代时，在清除标志未设置的情况下，为初始化处理器创建一个新的隔离区域。

公开(公告)号：US20240329993A1

公开(公告)日：2024-10-03

申请号：US18193232

申请日：2023-03-30

Applicant: Kameswar SUBRAMANIAM ,  Jason W. BRANDT ,  Gilbert NEIGER

Inventor： Kameswar SUBRAMANIAM ,  Jason W. BRANDT ,  Gilbert NEIGER

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30101 ,  G06F9/30185

Abstract: Techniques for allowing a control and/or status register to be read or written to in a user privilege level are described. An example of an instruction for user privilege read is to include one or more fields for an opcode, one or more fields for a source operand that is to store a control and/or status register address, and one or more fields for a destination register operand, wherein the opcode is to indicate that execution circuitry is to read data from the control and/or status register whose identity is stored in the source operand and write the data in the destination register operand responsive to access to the control and/or status register being allowed, wherein access to the control and/or status register is at least in part determined by data of an operating system controlled data structure indexed by the control and/or status register address.

公开(公告)号：US20220382885A1

公开(公告)日：2022-12-01

申请号：US17878322

申请日：2022-08-01

Applicant: David M. Durham ,  Michael LeMay ,  Ramya Jayaram Masti ,  Gilbert Neiger ,  Jason W. Brandt

Inventor： David M. Durham ,  Michael LeMay ,  Ramya Jayaram Masti ,  Gilbert Neiger ,  Jason W. Brandt

IPC: G06F21/60 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/48 ,  G06F21/72 ,  H04L9/06 ,  G06F12/06 ,  G06F12/0875 ,  G06F21/79 ,  G06F9/455 ,  G06F12/0811 ,  G06F21/12 ,  H04L9/08 ,  G06F12/14 ,  G06F9/32 ,  G06F9/50 ,  G06F12/02 ,  H04L9/14 ,  G06F21/62

Abstract: Technologies disclosed herein provide cryptographic computing with cryptographically encoded pointers in multi-tenant environments. An example method comprises executing, by a trusted runtime, first instructions to generate a first address key for a private memory region in the memory and generate a first cryptographically encoded pointer to the private memory region in the memory. Generating the first cryptographically encoded pointer includes storing first context information associated with the private memory region in first bits of the first cryptographically encoded pointer and performing a cryptographic algorithm on a slice of a first linear address of the private memory region based, at least in part, on the first address key and a first tweak, the first tweak including the first context information. The method further includes permitting a first tenant in the multi-tenant environment to access the first address key and the first cryptographically encoded pointer to the private memory region.

公开(公告)号：US20180196759A1

公开(公告)日：2018-07-12

申请号：US15912405

申请日：2018-03-05

Applicant: Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/1027 ,  G06F12/02 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1045 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US20150378941A1

公开(公告)日：2015-12-31

申请号：US14318508

申请日：2014-06-27

Applicant: Carlos V. Rozas ,  Ilya Alexandrovich ,  Gilbert Neiger ,  Francis X. McKeen ,  Ittai Anati ,  Vedvyas Shanbhogue ,  Shay Gueron

Inventor： Carlos V. Rozas ,  Ilya Alexandrovich ,  Gilbert Neiger ,  Francis X. McKeen ,  Ittai Anati ,  Vedvyas Shanbhogue ,  Shay Gueron

IPC: G06F13/24 ,  G06F12/08

CPC classification number: G06F13/24 ,  G06F12/08 ,  G06F12/0806 ,  G06F12/0875 ,  G06F21/00 ,  G06F21/71 ,  G06F21/85 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/62

Abstract: Instructions and logic interrupt and resume paging in secure enclaves. Embodiments include instructions, specify page addresses allocated to a secure enclave, the instructions are decoded for execution by a processor. The processor includes an enclave page cache to store secure data in a first cache line and in a last cache line for a page corresponding to the page address. A page state is read from the first or last cache line for the page when an entry in an enclave page cache mapping for the page indicates only a partial page is stored in the enclave page cache. The entry for a partial page may be set, and a new page state may be recorded in the first cache line when writing-back, or in the last cache line when loading the page when the instruction's execution is being interrupted. Thus the writing-back, or loading can be resumed.

Abstract translation: 指令和逻辑在安全飞地中中断和恢复寻呼。 实施例包括指令，指定分配给安全空间的页面地址，指令被解码以供处理器执行。 处理器包括用于将安全数据存储在与页面地址对应的页面的第一高速缓存行中的最后高速缓存行中的一个包围页面缓存。 当页面的飞地页面缓存映射中的条目仅指示部分页面存储在飞地页面缓存中时，从页面的第一个或最后一个高速缓存行读取页面状态。 可以设置部分页面的条目，并且当写回时可以在第一高速缓存行中记录新的页面状态，或者当指令的执行中断时在最后的高速缓存行中加载页面时。 因此，可以恢复回写或加载。

公开(公告)号：US20150199198A1

公开(公告)日：2015-07-16

申请号：US13997857

申请日：2011-12-29

Applicant: Adriaan Van De Ven ,  Baiju V. Patel ,  Asit K. Mallick ,  Gilbert Neiger ,  James S. Coke ,  Martin G. Dixon ,  Jason W. Brandt

Inventor： Adriaan Van De Ven ,  Baiju V. Patel ,  Asit K. Mallick ,  Gilbert Neiger ,  James S. Coke ,  Martin G. Dixon ,  Jason W. Brandt

IPC: G06F9/30

CPC classification number: G06F9/30189 ,  G06F9/30043 ,  G06F12/0292 ,  G06F12/1009 ,  G06F12/1491

Abstract: Apparatuses and methods for supervisor mode execution protection are disclosed. In one embodiment, a processor includes an interface to access a memory, execution hardware, and control logic. A region in the memory is user memory. The execution hardware is to execute an instruction. The control logic is to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode.

Abstract translation: 公开了用于监督模式执行保护的装置和方法。 在一个实施例中，处理器包括访问存储器，执行硬件和控制逻辑的接口。 存储器中的区域是用户存储器。 执行硬件是执行指令。 当指令存储在用户存储器中并且处理器处于主管模式时，控制逻辑是防止执行硬件执行指令。

公开(公告)号：US20150178202A1

公开(公告)日：2015-06-25

申请号：US14137432

申请日：2013-12-20

Applicant: Rajesh M. Sankaran ,  Neil M. Schaper ,  Joseph Nuzman ,  Larisa Novakovsky ,  Yen-Cheng Liu ,  Gilbert Neiger ,  Raj K. Ramanujan

Inventor： Rajesh M. Sankaran ,  Neil M. Schaper ,  Joseph Nuzman ,  Larisa Novakovsky ,  Yen-Cheng Liu ,  Gilbert Neiger ,  Raj K. Ramanujan

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032 ,  G06F2212/222

Abstract: An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.

Abstract translation: 描述了用于执行高速缓存行回写操作的装置和方法。 例如，方法的一个实施例包括：发起针对特定线性地址的高速缓存行回写操作; 确定由线性地址识别的脏高速缓存行是否存在于由多个高速缓存级别组成的高速缓存层级的任何高速缓存上; 如果脏缓存行存在于其中一个缓存中，则将脏缓存行写回内存; 以及响应地将所述脏高速缓存行维持或置于所述层次结构的至少第一高速缓存中的排他状态。

公开(公告)号：US20150135195A1

公开(公告)日：2015-05-14

申请号：US14076341

申请日：2013-11-11

Applicant: Atul KHARE ,  Leena PUTHIYEDATH ,  Asit MALLICK ,  Jim COKE ,  Michael MISHAELI ,  Gilbert NEIGER ,  Vivekananthan SANJEEPAN ,  Jason BRANDT

Inventor： Atul KHARE ,  Leena PUTHIYEDATH ,  Asit MALLICK ,  Jim COKE ,  Michael MISHAELI ,  Gilbert NEIGER ,  Vivekananthan SANJEEPAN ,  Jason BRANDT

IPC: G06F9/46

CPC classification number: G06F9/461 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/30101

Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.

Abstract translation: 公开了与压缩的上下文状态管理相关的发明的实施例。 在一个实施例中，处理器包括指令硬件和状态管理逻辑。 指令硬件是接收第一个保存指令和第二个保存指令。 状态管理逻辑是响应于第一保存指令，在第一保存区域中以未压缩格式保存上下文状态。 状态管理逻辑还响应于第二保存指令，在第二保存区域中以压缩格式保存压缩掩码和上下文状态，并在第二保存区域中设置压缩保存指示符。 状态管理逻辑还要响应于单个恢复指令，基于压缩保存指示符来确定是否从第一保存区域中的未压缩格式还原从第二保存中的压缩格式恢复上下文 区。