公开(公告)号：US20240232105A1

公开(公告)日：2024-07-11

申请号：US18413017

申请日：2024-01-15

Applicant: Netlist, Inc.

Inventor： Hyun Lee

IPC: G06F13/16 ,  G06F3/06 ,  G06F9/445 ,  G06F11/10 ,  G06F12/06 ,  G06F13/24 ,  G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C16/26 ,  G11C29/00 ,  G11C29/44 ,  G11C29/52

CPC classification number: G06F13/1694 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/445 ,  G06F11/1068 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/24 ,  G11C5/04 ,  G11C7/1063 ,  G11C29/52 ,  G11C5/00 ,  G11C7/1066 ,  G11C16/26 ,  G11C2029/4402 ,  G11C29/78 ,  G11C2207/2254

Abstract: A memory subsystem is operable with a memory controller of a host computer system via an interface. The memory subsystem comprises dynamic random access memory elements and a memory subsystem controller. The memory subsystem controller has an open drain output, and is configured to provide a first signaling interface via the open drain output during normal operations and a second signaling interface via the open drain output during an initialization operation. The second signaling interface is distinct from the first signaling interface and the initialization operation is distinct from any of the normal operations. The first signaling interface is used by the memory subsystem controller to indicate a parity error in response to a parity error having occurred during the normal operations. The second signaling interface is used by the memory subsystem controller to output a signal related to initialization operation sequences during the initialization operation.

公开(公告)号：US20230385192A1

公开(公告)日：2023-11-30

申请号：US18325081

申请日：2023-05-29

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0871 ,  G06F3/06 ,  G11C7/10 ,  G06F13/28 ,  G06F13/10 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F12/08 ,  G06F12/0871 ,  G06F3/061 ,  G11C7/1072 ,  G06F13/28 ,  G06F3/068 ,  G06F3/0685 ,  G06F13/10 ,  G06F12/0638 ,  G06F2212/205 ,  G06F3/0688 ,  G06F12/0897

Abstract: A memory module comprises dynamic random access memory (DRAM), Flash memory, and a module controller. The module controller is configured to receive data to be transferred from the DRAM to the Flash memory, compute first cyclic redundancy check (CRC) codes for the data, and write the data into the Flash memory. The module controller is further configured to read the data from the Flash memory, compute second CRC codes for the data read from the Flash memory, and transfer the data to the DRAM. The module controller is further configured to compare the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the Flash memory, read a data segment of the data from the DRAM that include the one or more erroneous data bits, correct the one or more erroneous data bits in the data segment, and write the data segment back into the DRAM.

公开(公告)号：US11232054B2

公开(公告)日：2022-01-25

申请号：US17328019

申请日：2021-05-24

Applicant: Netlist, Inc.

Inventor： Chi-She Chen ,  Jeffrey C. Solomon ,  Scott H. Milton ,  Jayesh Bhakta

IPC: G06F13/28 ,  G06F12/02 ,  G06F13/16 ,  G06F1/18 ,  G06F12/06 ,  G06F13/42 ,  G11C7/10 ,  G11C14/00 ,  G06F3/06 ,  G06F13/40

Abstract: In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.

公开(公告)号：US11200120B2

公开(公告)日：2021-12-14

申请号：US16517210

申请日：2019-07-19

Applicant: Netlist, Inc.

Inventor： Scott H. Milton ,  Jeffrey C. Solomon ,  Kenneth S. Post

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/07 ,  G11C16/34 ,  G11C29/42 ,  G11C29/44 ,  G11C29/04

Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.

公开(公告)号：US20210225415A1

公开(公告)日：2021-07-22

申请号：US17157903

申请日：2021-01-25

Applicant: Netlist, Inc.

Inventor： Hyun Lee

IPC: G11C5/06 ,  G11C7/10 ,  G11C7/12

Abstract: A DRAM package is operable on a memory module communicatively coupled to a system memory controller. The memory module includes a register device configurable to receive input command/address signals from the system memory controller and to output buffered command/address signals and data path control signals. The DRAM package includes stacked array dies and a control die. The control die includes data buffers, and is configurable to provide at least some of the buffered command/address signals to the stacked array dies, and to control the data buffers in response to the data path control signals to buffer data signals communicated between a selected array die of the stacked array dies and the system memory controller.

公开(公告)号：US10860506B2

公开(公告)日：2020-12-08

申请号：US16391151

申请日：2019-04-22

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F3/06 ,  G11C5/04 ,  G11C7/10 ,  G11C29/02 ,  G11C16/00 ,  G06F1/10 ,  G06F13/28 ,  G06F13/40 ,  G11C8/18 ,  G11C8/12 ,  G11C7/20 ,  G11C29/04

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

公开(公告)号：US20200042456A1

公开(公告)日：2020-02-06

申请号：US16539895

申请日：2019-08-13

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F12/0871

Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

公开(公告)号：US10324841B2

公开(公告)日：2019-06-18

申请号：US14445035

申请日：2014-07-28

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/08 ,  G06F12/0802 ,  G11C5/04 ,  G11C29/02 ,  G11C7/10

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in groups, each group including at least one memory device, while the data buffer control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits, a respective buffer circuit corresponding to a respective group of memory devices. The plurality of buffer circuits are distributed across a surface of the memory module such that each data buffer control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits include clock regeneration circuits to regenerate a clock signal received from the module control device and to provide regenerated clock signals to respective groups of memory devices.

公开(公告)号：US20190079683A1

公开(公告)日：2019-03-14

申请号：US15976321

申请日：2018-05-10

Applicant: Netlist, Inc.

Inventor： Hyun LEE

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0815

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0815 ,  G06F12/0868 ,  G06F2212/214 ,  G06F2212/621

Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.

公开(公告)号：US20190004985A1

公开(公告)日：2019-01-03

申请号：US15934416

申请日：2018-03-23

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Chi-She Chen ,  Jeffrey C. Solomon ,  Scott H. Milton ,  Jayesh Bhakta

IPC: G06F13/28 ,  G06F12/02 ,  G06F13/40 ,  G06F3/06 ,  G06F1/18 ,  G06F13/42 ,  G06F12/06 ,  G06F13/16 ,  G11C14/00 ,  G11C7/10

Abstract: A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.