公开(公告)号：US11194373B2

公开(公告)日：2021-12-07

申请号：US16853570

申请日：2020-04-20

Applicant: Intel Corporation

Inventor： Asma Al-Rawi ,  Federico Ardanaz ,  Jonathan M. Eastep ,  Nikhil Gupta ,  Ankush Varma ,  Krishnakanth V. Sistla ,  Ian M. Steiner

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  H04L12/12 ,  G06F1/3228 ,  G06F1/20

Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.

公开(公告)号：US20210208659A1

公开(公告)日：2021-07-08

申请号：US17207299

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Adwait Purandare ,  Ankush Varma ,  Nazar Haider ,  Daniela Kaufman ,  Gilad Bomstein ,  Shlomo Attias ,  Amit Gabai ,  Ariel Szapiro

IPC: G06F1/324 ,  G06F21/55 ,  G06F1/28

Abstract: An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (POnMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.

公开(公告)号：US20210064110A1

公开(公告)日：2021-03-04

申请号：US16633176

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Krishnakanth V. Sistla ,  Ankush Varma ,  Ariel Szapiro

IPC: G06F1/28 ,  G06F9/38

Abstract: In an embodiment, a processor includes a power control unit, a master processing engine, a set of slave processing engines, and a voltage regulator. The master processing engine is to, in response to a receipt of a change message from the power control unit, control the voltage regulator to adjust a voltage level provided to the master processing engine and the set of slave processing engines. Other embodiments are described and claimed.

公开(公告)号：US20200333867A1

公开(公告)日：2020-10-22

申请号：US16836686

申请日：2020-03-31

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Nir Rosenzweig ,  Krishnakanth V. Sistla ,  Ashish V. Choubal ,  Ankush Varma

IPC: G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/26

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

公开(公告)号：US10795853B2

公开(公告)日：2020-10-06

申请号：US15721822

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US10706004B2

公开(公告)日：2020-07-07

申请号：US15811848

申请日：2017-11-14

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Guy G. Sotomayor ,  Andrew D. Henroid ,  Robert E. Gough ,  Tod F. Schiff

IPC: G06F1/32 ,  G06F15/00 ,  G06F1/20 ,  G06F1/3234 ,  G06F9/455 ,  G06F9/50 ,  G06F1/26

Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

公开(公告)号：US10345884B2

公开(公告)日：2019-07-09

申请号：US15238717

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Martin T. Rowland ,  Chris Poirier ,  Eric J. Dehaemer ,  Avinash N. Ananthakrishnan ,  Jeremy J. Shrall ,  Xiuting C. Man ,  Stephen H. Gunther ,  Krishna K. Rangan ,  Devadatta V. Bodas ,  Don C. Soltis, Jr. ,  Hang T. Nguyen ,  Cyprian W. Woo ,  Thi Dang

IPC: G06F9/00 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/28

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

公开(公告)号：US20190102221A1

公开(公告)日：2019-04-04

申请号：US15720296

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunter ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US10228755B2

公开(公告)日：2019-03-12

申请号：US15281806

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Ankush Varma ,  Assaf Ganor ,  Nir Rosenzweig ,  David M. Pawlowski ,  Arik Gihon ,  Nadav Shulman

IPC: G06F1/28 ,  G06F1/32 ,  G06F1/3296

Abstract: In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.

公开(公告)号：US20180232024A1

公开(公告)日：2018-08-16

申请号：US15846161

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Krishnakanth Sistla ,  Martin Rowland ,  Efraim Rotem ,  Brian J. Griffith ,  Ankush Varma ,  Anupama Suryanarayanan

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/329 ,  Y02D10/152 ,  Y02D10/24

Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.