公开(公告)号：US10345884B2

公开(公告)日：2019-07-09

申请号：US15238717

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Martin T. Rowland ,  Chris Poirier ,  Eric J. Dehaemer ,  Avinash N. Ananthakrishnan ,  Jeremy J. Shrall ,  Xiuting C. Man ,  Stephen H. Gunther ,  Krishna K. Rangan ,  Devadatta V. Bodas ,  Don C. Soltis, Jr. ,  Hang T. Nguyen ,  Cyprian W. Woo ,  Thi Dang

IPC: G06F9/00 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/28

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

公开(公告)号：US10331614B2

公开(公告)日：2019-06-25

申请号：US15025988

申请日：2013-11-27

Applicant: INTEL CORPORATION ,  Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

Inventor： Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

IPC: G06F11/00 ,  G06F15/78 ,  G06F11/10 ,  G06F11/34 ,  G06F11/16

Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

公开(公告)号：US20160239460A1

公开(公告)日：2016-08-18

申请号：US15025988

申请日：2013-11-27

Applicant: INTEL CORPORATION

Inventor： Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

IPC: G06F15/78 ,  G06F11/16

CPC classification number: G06F15/7803 ,  G06F11/1068 ,  G06F11/108 ,  G06F11/1092 ,  G06F11/1662 ,  G06F11/3485 ,  G06F2201/805

Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

Abstract translation: 实现服务器架构的系统和方法可以方便计算机系统中的存储器组件的维护。 这些系统和方法采用非易失性存储/存储模块，其中包括可用于系统内存和大容量存储的非易失性存储器（NVM）以及固件存储器。 相应的NVM /存储模块可以被接收在计算机系统的前部或后部装载槽中。 该系统和方法进一步采用单插槽，双插槽或四插槽处理器，其中每个处理器通过一个或多个存储器和/或输入端可通信地耦合到布置在前端或后端装载机架中的至少一些NVM /存储模块 /输出（I / O）通道。 通过采用可以在计算机系统的前端或后端加载接收的NVM /存储模块，系统和方法提供了存储器组件在实现常规服务器架构的计算机系统中无法实现的可维护性。

公开(公告)号：US09417681B2

公开(公告)日：2016-08-16

申请号：US14697541

申请日：2015-04-27

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Martin T. Rowland ,  Chris Poirier ,  Eric J. Dehaemer ,  Avinash N. Ananthakrishnan ,  Jeremy J. Shrall ,  Xiuting C. Man ,  Stephen H. Gunther ,  Krishna K. Rangan ,  Devadatta V. Bodas ,  Don Soltis ,  Hang T. Nguyen ,  Cyprian W. Woo ,  Thi Dang

IPC: G06F15/177 ,  G06F1/32 ,  G06F1/00 ,  G06F1/20

CPC classification number: G06F1/3243 ,  G06F1/206 ,  G06F1/28 ,  G06F1/3206 ,  Y02D10/152

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

Abstract translation: 装置的一个实施例包括具有处理器和裸片上非易失性存储资源的半导体芯片。 片上非易失性存储器可以为处理器的相同性能状态的不同配置和处理器的使用情况存储不同的适当的性能相关信息。

公开(公告)号：US09502082B1

公开(公告)日：2016-11-22

申请号：US14748728

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Thi Dang ,  James S. Burns ,  Russell J. Wunderlich ,  Jagannath Coimbatore Premkumar

IPC: G11C7/00 ,  G11C5/14 ,  G11C14/00 ,  G06F1/26 ,  G11C11/22

CPC classification number: G11C5/147 ,  G06F1/26 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/14 ,  G11C11/005 ,  G11C11/2297 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: Methods, apparatuses, and systems may provide a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM. A switch, connected to an output of the sensor, controls power to the non-volatile RAM, and a voltage regulator regulates a voltage of the non-volatile RAM and the volatile RAM. One or more memory slots receive the non-volatile RAM and the volatile RAM, and a processor receives information from the sensor, and controls the voltage regulator based on the received information. The voltage regulator comprises a plurality of registers to store power consumption information of the non-volatile RAM and the volatile RAM.

Abstract translation: 方法，设备和系统可以提供传感器以监视非易失性随机存取存储器（RAM）和易失性RAM的功耗。 连接到传感器输出的开关控制非易失性RAM的电源，电压调节器调节非易失性RAM和易失性RAM的电压。 一个或多个存储器插槽接收非易失性RAM和易失性RAM，并且处理器从传感器接收信息，并且基于接收到的信息来控制电压调节器。 电压调节器包括多个寄存器以存储非易失性RAM和易失性RAM的功耗信息。