公开(公告)号：US20240219659A1

公开(公告)日：2024-07-04

申请号：US18089871

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Yiqun Bai ,  Bohan Shan ,  Kyle Jordan Arrington ,  Haobo Chen ,  Dingying Xu ,  Robert Alan May ,  Gang Duan ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4239 ,  H01Q1/2283

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240203853A1

公开(公告)日：2024-06-20

申请号：US18085281

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Hongxia Feng ,  Julianne Troiano ,  Dingying Xu ,  Matthew Tingey ,  Xiaoying Guo ,  Srinivas Venkata Ramanuja Pietambaram ,  Bai Nie ,  Gang Duan ,  Bin Mu ,  Kyle Mcelhinny ,  Ashay A. Dani ,  Leonel R. Arana

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L23/5384

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a substrate, a via, a build-up layer, a top layer, and one or more dies. The substrate can include a conductor coating. The via can be connected to the conductor coating. The build-up layer can be on the substrate. The build-up layer can define a channel that the via is formed within and insulate the via during operation of the electronic device. The top layer can be interproximal to the substrate and the via. The one or more dies can be connected to the via.

公开(公告)号：US20240194608A1

公开(公告)日：2024-06-13

申请号：US18080612

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Gang Duan ,  Rahul Manepalli ,  Srinivas Pietambaram ,  Brandon Marin ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L2221/68359

Abstract: An integrated circuit (IC) package comprises a first IC die having first metallization features, a second IC die having second metallization features, and a third IC die having third metallization features. A glass layer is between the third IC die and both of the first IC die and the second IC die. A plurality of first through vias extend through the glass layer, coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features. A plurality of second through vias extend through the glass layer. A dielectric material is around the third die and a package metallization is within the dielectric material. The package metallization is coupled to at least one of the first, second, or third IC die, and terminating at a plurality of package interconnect interfaces.

公开(公告)号：US20240186250A1

公开(公告)日：2024-06-06

申请号：US18061188

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Tarek A. Ibrahim ,  Suddhasattwa Nad ,  Gang Duan ,  Haobo Chen ,  Hiroki Tanaka

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/5386

Abstract: A microelectronic assembly includes a substrate comprising: a panel including glass and defining an opening therein; an interconnect bridge (IB) in the opening and including interconnect pathways and IB through vias (IBTVs); and electrically conductive structures at a lower surface of the substrate to electrically couple the substrate to another component, at least some of the electrically conductive structures coupled to the IBTVs to form respective vertical electrical connections between the lower surface of the substrate and an upper surface of the substrate; and an electronic component (EC) layer on the upper surface of the substrate, the EC layer including a first active EC (AEC) and a second AEC electrically coupled to one another through the interconnect pathways, at least one of the first AEC or the second AECs further electrically coupled to one or more of the at least some of the electrically conductive structures.

公开(公告)号：US11990427B2

公开(公告)日：2024-05-21

申请号：US17716947

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Gang Duan ,  Deepak Kulkarni ,  Rahul Manepalli ,  Xiaoying Guo

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US20240096809A1

公开(公告)日：2024-03-21

申请号：US17932624

申请日：2022-09-15

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Robert Alan May ,  Onur Ozkan ,  Ali Lehaf ,  Steve Cho ,  Gang Duan ,  Jieping Zhang ,  Rahul N. Manepalli ,  Ravindranath Vithal Mahajan ,  Hamid Azimi

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/5383 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/32 ,  H01L2224/13082 ,  H01L2224/1403 ,  H01L2224/16238 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/2201 ,  H01L2224/32225

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a surface including first conductive contacts and second conductive contacts, wherein the first conductive contacts have a first thickness and the second conductive contacts have a second thickness different than the first thickness; a first microelectronic component having third conductive contacts, wherein respective ones of the third conductive contacts are coupled to respective ones of the first conductive contacts by first interconnects, wherein the first interconnects include solder having a thickness between 2 microns and 35 microns; and a second microelectronic component having fourth conductive contact, wherein respective ones of the fourth conductive contacts are coupled to respective ones of the second conductive contacts by second interconnects, wherein the second interconnects include solder having a thickness between 5 microns and 50 microns.

公开(公告)号：US20240079339A1

公开(公告)日：2024-03-07

申请号：US17929045

申请日：2022-09-01

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Benjamin T. Duong ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L23/481 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.

公开(公告)号：US20240079335A1

公开(公告)日：2024-03-07

申请号：US17939824

申请日：2022-09-07

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L25/0655 ,  H01L2224/08225

Abstract: In one embodiment, an integrated circuit device includes a first layer having input/output (IO) hub circuitry to interconnect a plurality of integrated circuit dies, and a second layer having a plurality of integrated circuit dies electrically connected to the IO hub circuitry. The first layer may include glass, and the IO hub circuitry may be in a die embedded within the first layer. The integrated circuit dies may be electrically connected to the IO hub circuitry through an interposer.

公开(公告)号：US11923312B2

公开(公告)日：2024-03-05

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Srinivas Pietambaram ,  Jesse Jones ,  Yosuke Kanaoka ,  Hongxia Feng ,  Dingying Xu ,  Rahul Manepalli ,  Sameer Paital ,  Kristof Darmawikarta ,  Yonggang Li ,  Meizi Jiao ,  Chong Zhang ,  Matthew Tingey ,  Jung Kyu Han ,  Haobo Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20230395445A1

公开(公告)日：2023-12-07

申请号：US17833650

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Tarek A. Ibrahim ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Gang Duan ,  Suddhasattwa Nad ,  Yi Yang ,  Benjamin T. Duong ,  Junxin Wang ,  Sameer R. Paital

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H05K1/03 ,  H05K3/40

CPC classification number: H01L23/15 ,  H01L23/49827 ,  H01L21/486 ,  H05K1/0306 ,  H05K3/4061

Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.