公开(公告)号：US10571501B2

公开(公告)日：2020-02-25

申请号：US15459248

申请日：2017-03-15

Applicant: Intel Corporation

Inventor： Xiaoning Ye ,  Kai Xiao

IPC: G01R27/28

Abstract: Technologies for verifying a de-embedder for interconnect measurement include a verification compute device. The verification compute device is to measure a first signal transmitted through a single device under test and measure a second signal transmitted through a duplicated set of devices under test. Each device under test in the duplicated set is substantially identical to the single device under test. Additionally, the verification compute device is to apply a de-embedder to the measured first signal to remove an effect of test fixtures on the measured first signal, apply the de-embedder to the measured second signal to remove the effect of the test fixtures on the measured second signal, concatenate the de-embedded first signal with itself to generate a concatenated de-embedded first signal, and compare the concatenated de-embedded first signal with the de-embedded second signal to determine whether the concatenated de-embedded first signal matches the de-embedded second signal.

公开(公告)号：US10249924B2

公开(公告)日：2019-04-02

申请号：US14752642

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Raul Enriquez Shibayama ,  Gong Ouyang ,  Jose Diego Guillen Gonzalez ,  Beom-Taek Lee

IPC: G06F3/041 ,  H01P3/08 ,  H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H05K3/42 ,  H01P5/02

Abstract: Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.

公开(公告)号：US10242486B2

公开(公告)日：2019-03-26

申请号：US15488837

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Michael Apodaca ,  Kai Xiao ,  Altug Koker ,  Jeffery S. Boles ,  Adam T. Lake ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  James M. Holland ,  Prasoonkumar Surti ,  Jonathan Kennedy ,  Louis Feng ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06T15/06 ,  G06T15/00 ,  G06T19/00 ,  G06F3/01 ,  H04S7/00 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10

Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.

公开(公告)号：US10223773B2

公开(公告)日：2019-03-05

申请号：US15477003

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Tomer Bar-On ,  Hugues Labbe ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Johannes Guenther ,  Abhishek R. Appu ,  Joydeep Ray ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall

IPC: G06T5/00 ,  G06T1/20 ,  G06T15/00 ,  G06T15/50

Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.

公开(公告)号：US20180293698A1

公开(公告)日：2018-10-11

申请号：US15483641

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Abhishek Venkatesh ,  Prasoonkumar Surti ,  Slawomir Grajewski ,  Louis Feng ,  Kai Xiao ,  Tomasz Janczak ,  Devan Burke ,  Travis T. Schluessler

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.

公开(公告)号：US20180286016A1

公开(公告)日：2018-10-04

申请号：US15477003

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Tomer Bar-On ,  Hugues Labbe ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Johannes Guenther ,  Abhishek R. Appu ,  Joydeep Ray ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall

IPC: G06T5/00 ,  G06T15/50 ,  G06T15/00 ,  G06T1/20

CPC classification number: G06T5/002 ,  G06T1/20 ,  G06T9/00 ,  G06T11/40 ,  G06T15/005 ,  G06T15/503 ,  G06T2200/12

Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.

公开(公告)号：US20180191374A1

公开(公告)日：2018-07-05

申请号：US15851747

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Md. Mohiuddin Mazumder ,  Subas Bastola ,  Kai Xiao

IPC: H03M13/11 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42

CPC classification number: H03M13/11 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/0026

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US20180174940A1

公开(公告)日：2018-06-21

申请号：US15383858

申请日：2016-12-19

Applicant: Intel Corporation

Inventor： Shelby Ferguson ,  Gong Ouyang ,  Russell S. Aoki ,  Zhichao Zhang ,  Kai Xiao

IPC: H01L23/34 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L23/345 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225

Abstract: Disclosed herein are fine-featured traces for integrated circuit (IC) package support structures, and related systems, devices, and methods. For example, a device may include a printed circuit board (PCB) having an insulating material and a heater trace on the insulating material. In some embodiments, the heater trace may have a section with a width less than 3.5 mils. In some embodiments, a section of the heater trace may be adjacent to a burned portion of the insulating material.

公开(公告)号：US09935353B2

公开(公告)日：2018-04-03

申请号：US14862159

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Gong Ouyang ,  Shaowu Huang ,  Kai Xiao

IPC: H01P3/08 ,  H01P11/00 ,  H01P3/04 ,  H05K1/02

CPC classification number: H01P3/081 ,  H01P3/04 ,  H01P11/003 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0245 ,  H05K2201/09036 ,  H05K2201/09872

Abstract: A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient medium (e.g., air, another gas, vacuum) of a lower dielectric loss than the conductor's surrounding dielectric. The trench may be made by any suitably precise method such as laser scribing, chemical etching or mechanical displacement. A thin layer of dielectric may be left on the sides of the conductor to prevent oxidation or other reactions that may reduce conductivity. When the conductor carries a signal, part of an electric and/or magnetic field that would ordinarily travel through the surrounding dielectric encounters the low-loss ambient medium (e.g. air) in the trench. The effective dielectric loss surrounding the conductor is lowered, reducing signal attenuation and crosstalk, particularly at high frequencies.

公开(公告)号：US09922751B2

公开(公告)日：2018-03-20

申请号：US15088924

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Gong Ouyang ,  Kai Xiao ,  Eric J. Li ,  Kemal Aygun

IPC: H01B7/00 ,  H01B7/02 ,  H05K9/00 ,  H01B13/08 ,  H01B13/22

CPC classification number: H01B7/0241 ,  H01B11/1856 ,  H01B11/20 ,  H01B13/08 ,  H01B13/22 ,  H05K9/0098

Abstract: A helically wound insulated twinax cable reduces cable dielectric loss by increasing the percentage of air in the dielectric filler surrounding the signal conductors. The helical insulator wire winding further provides mechanical support and reduces the risk of creating an electrical short-circuit. This will improve differential signaling capability of the two-conductor cable and enable longer cable range.