公开(公告)号：US20200312907A1

公开(公告)日：2020-10-01

申请号：US16367126

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Daniel Ouellette ,  Christopher Wiegand ,  Justin Brockman ,  Tofizur Rahman ,  Oleg Golonzka ,  Angeline Smith ,  Andrew Smith ,  James Pellegren ,  Aaron Littlejohn ,  Michael Robinson ,  Huiying Liu

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01F10/32 ,  H01L43/12 ,  G11C11/16 ,  H01F41/34

Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.

公开(公告)号：US20200006632A1

公开(公告)日：2020-01-02

申请号：US16024427

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Daniel Ouellette ,  Justin Brockman ,  Tofizur Rahman ,  Angeline Smith ,  Andrew Smith ,  Christopher Wiegand ,  Oleg Golonzka

IPC: H01L43/02 ,  H01L27/22 ,  H01F10/32

Abstract: A memory device includes a bottom electrode, a conductive layer such as an alloy including ruthenium and tungsten above the bottom electrode and a perpendicular magnetic tunnel junction (pMTJ) on the conductive layer. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet on the tunnel barrier. The memory device further includes a synthetic antiferromagnetic (SAF) structure that is ferromagnetically coupled with the fixed magnet to pin a magnetization of the fixed magnet. The conductive layer has a crystal texture which promotes high quality FCC crystal texture in the SAF structure and improves perpendicular magnetic anisotropy of the fixed magnet.

公开(公告)号：US20190288190A1

公开(公告)日：2019-09-19

申请号：US16430201

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/10 ,  H01F10/32 ,  H01F41/30 ,  H01L43/08

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.

公开(公告)号：US10418415B2

公开(公告)日：2019-09-17

申请号：US16069165

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Oleg Golonzka ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Kevin P. O'Brien ,  Kaan Oguz ,  Tahir Ghani ,  Satyarth Suri

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01F41/32 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213

Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.

公开(公告)号：US20180248114A1

公开(公告)日：2018-08-30

申请号：US15755444

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/08 ,  H01L43/02 ,  H01F10/32 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12 ,  H01F41/30

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular MTJ material stacks with free magnetic layers are magnetically coupled through a metal material layer for improved stability and low damping. In some advantageous embodiments, layers of a free magnetic material stack are magnetically coupled through a coupling layer of a metal comprising at least molybdenum (Mo). The Mo may be in pure form or alloyed with other constituents.

公开(公告)号：US20180097003A1

公开(公告)日：2018-04-05

申请号：US15828259

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Joseph Steigerwald ,  Tahir Ghani ,  Oleg Golonzka

IPC: H01L27/092 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

公开(公告)号：US09318694B2

公开(公告)日：2016-04-19

申请号：US14140758

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Daniel Lamborn ,  Oleg Golonzka ,  Christopher Wiegand

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Methods of forming a memory device structure are described. Those methods may include forming a non-conductive spacer material on a top electrode of a magnetic tunnel junction structure, and then forming a highly selective material on the non-conductive spacer material of the magnetic tunnel junction prior to etching a bottom electrode of the magnetic tunnel junction.

Abstract translation: 描述形成存储器件结构的方法。 这些方法可以包括在磁性隧道结结构的顶部电极上形成非导电间隔物材料，然后在蚀刻磁性体的底部电极之前在磁性隧道结的非导电间隔物材料上形成高选择性材料 隧道交界处。

公开(公告)号：US09293579B2

公开(公告)日：2016-03-22

申请号：US14284808

申请日：2014-05-22

Applicant: INTEL CORPORATION

Inventor： Bernhard Sell ,  Oleg Golonzka

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.