公开(公告)号：US20220059704A1

公开(公告)日：2022-02-24

申请号：US16999819

申请日：2020-08-21

Applicant: INTEL CORPORATION

Inventor： Chieh-jen Ku ,  Bernhard Sell ,  Pei-hua Wang ,  Christopher J. Wiegand

IPC: H01L29/786 ,  H01L27/108

Abstract: Disclosed herein are transistor cap-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor cap-channel arrangement may include a channel material having a conductivity type; an insulating material; and a cap material between the channel material and the insulating material, wherein the cap material is different from the channel material and the insulating material, and the cap material has a conductivity type that is a same conductivity type as the channel material.

公开(公告)号：US11063151B2

公开(公告)日：2021-07-13

申请号：US16481028

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Jeffrey S. Leib ,  Daniel B. Bergstrom ,  Christopher J. Wiegand

IPC: H01L23/532 ,  H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8234

Abstract: Metal chemical vapor deposition approaches for fabricating wrap-around contacts, and semiconductor structures having wrap-around metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor feature above a substrate. A dielectric layer is over the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-flat topography. A metallic contact material is directly on the portion of the semiconductor feature. The metallic contact material is conformal with the non-flat topography of the portion of the semiconductor feature. The metallic contact material has a total atomic composition including 95% or greater of a single metal species.

公开(公告)号：US10580970B2

公开(公告)日：2020-03-03

申请号：US15755444

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32 ,  H01F41/30 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular MTJ material stacks with free magnetic layers are magnetically coupled through a metal material layer for improved stability and low damping. In some advantageous embodiments, layers of a free magnetic material stack are magnetically coupled through a coupling layer of a metal comprising at least molybdenum (Mo). The Mo may be in pure form or alloyed with other constituents.

公开(公告)号：US20200006635A1

公开(公告)日：2020-01-02

申请号：US16024599

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tofizur Rahman ,  Christopher J. Wiegand ,  Justin S. Brockman ,  Daniel G. Ouellette ,  Angeline K. Smith ,  Andrew Smith ,  Pedro A. Quintero ,  Juan G. Alzate-Vinasco ,  Oleg Golonzka

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

Abstract: A memory device includes a perpendicular magnetic tunnel junction (pMTJ) stack, between a bottom electrode and a top electrode. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet structure on the tunnel barrier. The free magnet structure includes a first free magnet on the tunnel barrier and a second free magnet above the first free magnet, wherein at least a portion of the free magnet proximal to an interface with the free magnet includes a transition metal. The free magnet structure having a transition metal between the first and the second free magnets advantageously improves the switching efficiency of the MTJ, while maintaining a thermal stability of at least 50 kT.

公开(公告)号：US20180287050A1

公开(公告)日：2018-10-04

申请号：US15755488

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Prashanth P. Madras ,  MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Oleg Golonzka ,  Kevin P. O'Brien ,  Mark L. Doczy ,  Brian S. Doyle ,  Tahir Ghani ,  Kaan Oguz

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32 ,  G11C11/16 ,  H01L27/22

Abstract: MTJ material stacks with a laterally strained free magnetic layer, STTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular pMTJ material stacks included free magnetic layers that are compressively strained laterally by a surrounding material, which increases coercive field strength for a more stable device. In some embodiments, a pMTJ material stack is encased in a compressive-stressed material. In some further embodiments, a pMTJ material stack is encased first in a dielectric shell, permitting a conductive material to be deposited over the shell as the compressive-stressed, strain-inducing material layer.

公开(公告)号：US20180248115A1

公开(公告)日：2018-08-30

申请号：US15755446

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F10/32 ,  G11C11/16 ,  H01F41/30

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01F10/30 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/302 ,  H01F41/304 ,  H01L27/222 ,  H01L43/10 ,  H01L43/12

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include one or more electrode interface material layers disposed between a an electrode metal, such as TiN, and a seed layer of an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. The electrode interface material layers may include either or both of a Ta material layer or CoFeB material layer. In some Ta embodiments, a Ru material layer may be deposited on a TiN electrode surface, followed by the Ta material layer. In some CoFeB embodiments, a CoFeB material layer may be deposited directly on a TiN electrode surface, or a Ta material layer may be deposited on the TiN electrode surface, followed by the CoFeB material layer.

公开(公告)号：US20230369508A1

公开(公告)日：2023-11-16

申请号：US17742644

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Timothy Jen ,  Prem Chanani ,  Cheng Tan ,  Brian Wadsworth ,  Andre Baran ,  James Pellegren ,  Christopher J. Wiegand ,  Van H. Le ,  Abhishek Anil Sharma ,  Shailesh Kumar Madisetti ,  Xiaojun Weng

IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L29/78687 ,  H01L23/5283 ,  H01L29/7869 ,  H01L27/10814

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region. One example application of the techniques is with respect to forming backend (within the interconnect region) memory structures configured with multilayer and/or concentration gradient TFTs.

公开(公告)号：US11183432B2

公开(公告)日：2021-11-23

申请号：US16844588

申请日：2020-04-09

Applicant: Intel Corporation

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US11107908B2

公开(公告)日：2021-08-31

申请号：US16306540

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Anurag Chaudhry ,  Dmitri E. Nikonov ,  Jasmeet S. Chawla ,  Christopher J. Wiegand ,  Kanwaljit Singh ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/775 ,  H01L29/10 ,  H01L29/739 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L21/285 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/47 ,  H01L29/78

Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.

公开(公告)号：US11018222B1

公开(公告)日：2021-05-25

申请号：US16728088

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Daniel B. O'Brien ,  Christopher J. Wiegand ,  Lukas M. Baumgartel ,  Oleg Golonzka ,  Dan S. Lavric ,  Daniel B. Bergstrom ,  Jeffrey S. Leib ,  Timothy Michael Duffy ,  Dax M. Crum

IPC: H01L29/06 ,  H01L23/00 ,  B82B1/00

Abstract: Disclosed herein are structures, methods, and assemblies related to metallization in integrated circuit (IC) structures. For example, in some embodiments, an IC structure may include a first nanowire in a metal region and a second nanowire in the metal region. A distance between the first nanowire and the second nanowire may be less than 5 nanometers, and the metal region may include tungsten between the first nanowire and the second nanowire.