公开(公告)号：US11941534B2

公开(公告)日：2024-03-26

申请号：US16729379

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Gurpreet Singh Kalsi ,  Anant V. Nori ,  Christopher Justin Hughes ,  Sreenivas Subramoney ,  Damla Senol

IPC: G06N3/123 ,  G06F9/30 ,  G06F15/78 ,  G06F15/80 ,  G06F40/45 ,  G16B30/00 ,  G16B30/10 ,  G06F17/00

CPC classification number: G06N3/123 ,  G06F9/30036 ,  G06F15/78 ,  G06F15/8053 ,  G06F15/8061 ,  G06F40/45 ,  G16B30/00 ,  G16B30/10 ,  G06F17/00

Abstract: A system is provided that includes a bit vector-based distance counter circuitry configured to generate one or more bit vectors encoded with information about potential matches and edits between a read and a reference genome, wherein the read comprises an encoding of a fragment of deoxyribonucleic acid (DNA) encoded via bases G, A, T, C. The system further includes a bit vector-based traceback circuitry configured to divide the reference genome into one or more windows and to use the plurality of bit vectors to generate a traceback output for each of the one or more windows, wherein the traceback output comprises a match, a substitution, an insert, a delete, or a combination thereof, between the read and the one or more windows.

公开(公告)号：US20230409481A1

公开(公告)日：2023-12-21

申请号：US18320780

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Stanislav Shwartsman ,  Anant Nori ,  Shankar Balachandran ,  Elad Shtiegmann ,  Vineeth Mekkat ,  Manjunath Shevgoor ,  Sourabh Alurkar

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

公开(公告)号：US20230333999A1

公开(公告)日：2023-10-19

申请号：US18339762

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Om Ji Omer ,  Anirud Thyagharajan ,  Sreenivas Subramoney

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Systems, apparatuses and methods may provide for technology that includes a chip having a memory structure including compute hardware, a plurality of address decoders coupled to the compute hardware, and a hierarchical interconnect fabric coupled to the plurality of address decoders, and direct memory address (DMA) hardware positioned adjacent to one or more of the plurality of address decoders, wherein the DMA hardware is to conduct on-chip transfers of intermediate state data via the hierarchical interconnect fabric. Additionally, the chip may include logic to allocate address space in the chip to intermediate state data and store the intermediate state data to the allocated address space.

公开(公告)号：US20230161626A1

公开(公告)日：2023-05-25

申请号：US18049509

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Gurpreet S. Kalsi ,  Om Ji Omer ,  Prashant Laddha ,  Kamlesh R. Pillai ,  Anirud Thyagharajan ,  Meenal Kudalkar ,  Krishnan Ananthanarayanan ,  Sreenivas Subramoney

IPC: G06F9/50 ,  G06T1/60

CPC classification number: G06F9/5027 ,  G06T1/60

Abstract: An embodiment of an apparatus comprises a hardware accelerator to perform a three-dimensional (3D) point cloud data access operation, and circuitry coupled to the hardware accelerator to control the hardware accelerator to perform the 3D point cloud data access operation in response to a request. Other embodiments are disclosed and claimed.

公开(公告)号：US20220197799A1

公开(公告)日：2022-06-23

申请号：US17133615

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Adarsh Chauhan ,  Vinodh Gopal ,  Vedvyas Shanbhogue ,  Sreenivas Subramoney ,  Wajdi Feghali

IPC: G06F12/0811 ,  G06F12/0862 ,  G06F12/0895 ,  G06F9/38

Abstract: Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220113974A1

公开(公告)日：2022-04-14

申请号：US17561029

申请日：2021-12-23

Applicant: INTEL CORPORATION

Inventor： Om Ji Omer ,  Gurpreet Singh Kalsi ,  Anirud Thyagharajan ,  Saurabh Jain ,  Kamlesh R. Pillai ,  Sreenivas Subramoney ,  Avishaii Abuhatzera

IPC: G06F9/38 ,  G06F9/30

Abstract: A memory architecture includes processing circuits co-located with memory subarrays for performing computations within the memory architecture. The memory architecture includes a plurality of decoders in hierarchical levels that include a multicast capability for distributing data or compute operations to individual subarrays. The multicast may be configurable with respect to individual fan-outs at each hierarchical level. A computation workflow may be organized into a compute supertile representing one or more “supertiles” of input data to be processed in the compute supertile. The individual data tiles of the input data supertile may be used by multiple compute tiles executed by the processing circuits of the subarrays, and the data tiles multicast to the respective processing circuits for efficient data loading and parallel computation.

公开(公告)号：US20220091852A1

公开(公告)日：2022-03-24

申请号：US17028387

申请日：2020-09-22

Applicant: Intel Corporation

Inventor： Saurabh Gupta ,  Niranjan Kumar Soundarajan ,  Sreenivas Subramoney ,  Ragavendra Natarajan

IPC: G06F9/38 ,  G06F9/30

Abstract: Methods and apparatus relating to Instruction Set Architecture (ISA) and/or microarchitecture for early pipeline re-steering using load address prediction to mitigate branch misprediction penalties are described. In an embodiment, decode circuitry decodes a load instruction and Load Address Predictor (LAP) circuitry issues a load prefetch request to memory for data for a load operation of the load instruction. Compute circuitry executes an outcome for a branch operation of the load instruction based on the data from the load prefetch request. And re-steering circuitry transmits a signal to cause flushing of data associated with the load instruction in response to a mismatch between the outcome for the branch operation and a stored prediction value for the branch. Other embodiments are also disclosed and claimed.

公开(公告)号：US11238309B2

公开(公告)日：2022-02-01

申请号：US16232778

申请日：2018-12-26

Applicant: INTEL CORPORATION

Inventor： Dipan Kumar Mandal ,  Gurpreet Kalsi ,  Om J Omer ,  Prashant Laddha ,  Sreenivas Subramoney

IPC: G06K9/62 ,  G06T7/246 ,  G06K9/38 ,  G06K9/46 ,  G06T7/579

Abstract: An example apparatus for selecting keypoints in image includes a keypoint detector to detect keypoints in a plurality of received images. The apparatus also includes a score calculator to calculate a keypoint score for each of the detected keypoints based on a descriptor score indicating descriptor invariance. The apparatus includes a keypoint selector to select keypoints based on the calculated keypoint scores. The apparatus also further includes a descriptor calculator to calculate descriptors for each of the selected keypoints. The apparatus also includes a descriptor matcher to match corresponding descriptors between images in the plurality of received images. The apparatus further also includes a feature tracker to track a feature in the plurality of images based on the matched descriptors.

公开(公告)号：US20210110187A1

公开(公告)日：2021-04-15

申请号：US17131121

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Kamlesh Pillai ,  Gurpreet Singh Kalsi ,  Sreenivas Subramoney ,  Prashant Laddha ,  Om Ji Omer

IPC: G06K9/00 ,  G06F7/544 ,  G06N3/04 ,  G06K9/62 ,  G06T1/60

Abstract: Systems, apparatuses and methods may provide for technology that decodes data via an instruction that indicates a number of rulebooks to be processed, an input feature size, an output feature size, and a plurality of feature map base addresses, rearranges spatially distributed voxel output feature maps in the decoded data based on weight planes, and performs a channel-wise multiply-accumulate (MAC) operation on the rearranged spatially distributed voxel output feature maps to obtain an output, wherein the channel-wise MAC operation is performed as partial accumulations by a plurality of processing elements.

公开(公告)号：US20200285580A1

公开(公告)日：2020-09-10

申请号：US16618070

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Lavanya Subramanian ,  Sreenivas Subramoney ,  Anant Vithal Nori

IPC: G06F12/0842 ,  G11C11/406 ,  G11C11/4096

Abstract: In one embodiment, an apparatus comprises a processor and a memory controller. The processor is to identify a memory access operation associated with a memory location of a memory. The processor is further to determine that a cache memory does not contain data associated with the memory location. The processor is further to send a memory access notification to a memory controller via a first transmission path. The processor is further to send a memory access request to the memory controller via a second transmission path, wherein the second transmission path is slower than the first transmission path. The memory controller is to receive the memory access notification via the first transmission path, and send a memory activation request based on the memory access notification, wherein the memory activation request comprises a request to activate a memory bank associated with the memory location.