公开(公告)号：US10366024B2

公开(公告)日：2019-07-30

申请号：US15149219

申请日：2016-05-09

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/28 ,  G06F13/40 ,  G06F12/1027 ,  G06F12/1081

Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system is configured to purge a device table cache (DTC) in response to the processor executing the program instructions. An operating system runs on the synchronous I/O computing system and issues a synchronous I/O command indicating a request to perform a device table entry transaction that has a total data length to be transferred. A device table entry is selected from a device table, loaded into the DTC, and data packets corresponding to the device table entry transaction are transferred using the selected device table entry. A host bridge processor monitors the data packets transferred using the selected table entry, and automatically purges the selected device table entry from the DTC in response to determining the transferred data packets match the total data length.

公开(公告)号：US20190179572A1

公开(公告)日：2019-06-13

申请号：US15834133

申请日：2017-12-07

Applicant: International Business Machines Corporation

Inventor： Jonathan Bradbury ,  Matthias Klein ,  Ashutosh Misra ,  Anthony Sofia

IPC: G06F3/06

Abstract: A system and method to manage a non-universal encoder and a universal encoder for compression of data include receiving the data. The data includes symbols. The method also includes subdividing the data into a first set of data blocks and a second set of data blocks and generating a non-universal encoder using the first set of data blocks. The non-universal encoder includes first codes. Each of the first codes corresponds to one of the symbols in the first set of data blocks only and at least one of the first codes includes fewer bits than the symbol corresponding to the at least one of the first codes. The method further includes compressing the second set of data blocks using at least the non-universal encoder.

公开(公告)号：US20190163444A1

公开(公告)日：2019-05-30

申请号：US15827831

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jörg-Stephan Vogt ,  Norbert Hagspiel ,  Christian Jacobi ,  Matthias Klein

IPC: G06F7/24 ,  G06F9/30 ,  G06F9/54 ,  G06F13/16 ,  H03K19/177

Abstract: A compare unit includes an array including a plurality of buffer pairs to receive records on one level of a plurality of levels of a hierarchical structure. A comparator is coupled to the array, and the comparator includes one input to receive one beat of one record from one buffer of a selected buffer pair of the plurality of buffer pairs coupled to the comparator. The comparator further includes another input to receive another beat of another record from another buffer of the selected buffer pair, and logic coupled to the one input and the other input to compare the one beat and the other beat to obtain a winner beat of the compare.

公开(公告)号：US20190018775A1

公开(公告)日：2019-01-17

申请号：US15651543

申请日：2017-07-17

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Timothy C. Bronson ,  Matthias Klein ,  Pak-kin Mak ,  Vesselina K. Papazova ,  Robert J. Sonnelitter, III ,  Lahiruka S. Winter

IPC: G06F12/0831 ,  G06F13/16

CPC classification number: G06F12/0831 ,  G06F13/1615 ,  G06F2212/60 ,  G06F2212/621

Abstract: Embodiments include methods, systems and computer program products method for maintaining ordered memory access with parallel access data streams associated with a distributed shared memory system. The computer-implemented method includes performing, by a first cache, a key check, the key check being associated with a first ordered data store. A first memory node signals that the first memory node is ready to begin pipelining of a second ordered data store into the first memory node to an input/output (I/O) controller. A second cache returns a key response to the first cache indicating that the pipelining of the second ordered data store can proceed. The first memory node sends a ready signal indicating that the first memory node is ready to continue pipelining of the second ordered data store into the first memory node to the I/O controller, wherein the ready signal is triggered by receipt of the key response.

公开(公告)号：US20180374522A1

公开(公告)日：2018-12-27

申请号：US15629923

申请日：2017-06-22

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Sascha Junghans ,  Matthias Klein ,  Pak-Kin Mak ,  Robert J. Sonnelitter, III ,  Chad G. Wilson

IPC: G11C8/06 ,  G06F3/06 ,  G06F13/16

Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

公开(公告)号：US20180357171A1

公开(公告)日：2018-12-13

申请号：US16103253

申请日：2018-08-14

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Matthias Klein ,  Eric N. Lais

IPC: G06F12/0831 ,  G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/0831 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/621 ,  G06F2212/68

Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transfer data packets corresponding to the transaction. The program instructions further command the operating system to automatically purge the address translation cache entries associated with a transaction in response to detect that the transaction is completed.

公开(公告)号：US10095620B2

公开(公告)日：2018-10-09

申请号：US15196503

申请日：2016-06-29

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Matthias Klein ,  Eric N. Lais

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0831 ,  G06F12/1027 ,  G06F12/1009

Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transfer data packets corresponding to the transaction. The program instructions further command the operating system to automatically purge the address translation cache entries associated with a transaction in response to detect that the transaction is completed.

公开(公告)号：US20180203817A1

公开(公告)日：2018-07-19

申请号：US15923004

申请日：2018-03-16

Applicant: International Business Machines Corporation

Inventor： Matthias Klein ,  Eric N. Lais ,  Darwin W. Norton, JR.

IPC: G06F13/28 ,  G06F13/40 ,  G06F12/0891 ,  G06F12/1009

CPC classification number: G06F13/28 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/4027 ,  G06F2212/60

Abstract: A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in response to the processor executing the program instructions to perform issuing, via an operating system running on the computing system, a command indicating a request to perform an I/O transaction requiring a translation entry. A host bridge monitors a total data length of the address translation entry to be transferred during the I/O transaction. An address translation entry is selected from an address translation table, loaded into the address translation cache, and data corresponding to the I/O transaction is transferred using the selected address translation entry. The host bridge automatically purges the selected address translation entry from the address translation cache in response to determining the transferred amount of data matches the total data length for the address translation entry.

公开(公告)号：US20170371816A1

公开(公告)日：2017-12-28

申请号：US15193905

申请日：2016-06-27

Applicant: International Business Machines Corporation

Inventor： Matthias Klein ,  Eric N. Lais ,  Darwin W. Norton, JR.

IPC: G06F13/28 ,  G06F12/0891 ,  G06F12/1009 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/4027 ,  G06F2212/60

Abstract: A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in response to the processor executing the program instructions to perform issuing, via an operating system running on the computing system, a command indicating a request to perform an I/O transaction requiring a translation entry. A host bridge monitors a total data length of the address translation entry to be transferred during the I/O transaction. An address translation entry is selected from an address translation table, loaded into the address translation cache, and data corresponding to the I/O transaction is transferred using the selected address translation entry. The host bridge automatically purges the selected address translation entry from the address translation cache in response to determining the transferred amount of data matches the total data length for the address translation entry.

公开(公告)号：US20170322894A1

公开(公告)日：2017-11-09

申请号：US15149219

申请日：2016-05-09

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/28 ,  G06F13/40 ,  G06F12/0813 ,  G06F12/0891

CPC classification number: G06F13/28 ,  G06F12/1027 ,  G06F12/1081 ,  G06F13/4027 ,  G06F2212/60 ,  G06F2213/28

Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system is configured to purge a device table cache (DTC) in response to the processor executing the program instructions. An operating system runs on the synchronous I/O computing system and issues a synchronous I/O command indicating a request to perform a device table entry transaction that has a total data length to be transferred. A device table entry is selected from a device table, loaded into the DTC, and data packets corresponding to the device table entry transaction are transferred using the selected device table entry. A host bridge processor monitors the data packets transferred using the selected table entry, and automatically purges the selected device table entry from the DTC in response to determining the transferred data packets match the total data length.