公开(公告)号：US20220416024A1

公开(公告)日：2022-12-29

申请号：US17903914

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： Glenn GLASS ,  Anand MURTHY ,  Biswajeet GUHA ,  Dax CRUM ,  Patrick KEYS ,  Tahir GHANI ,  Susmita GHOSE ,  Ted COOK, JR.

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/027 ,  H01L27/092 ,  H01L21/683 ,  H01L21/8238

Abstract: Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US20220415881A1

公开(公告)日：2022-12-29

申请号：US17357754

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Rui MA ,  Kalyan KOLLURU ,  Nicholas THOMSON ,  Ayan KAR ,  Benjamin ORR ,  Nathan JACK ,  Biswajeet GUHA ,  Brian GREENE ,  Chung-Hsun LIN

IPC: H01L27/02

Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

公开(公告)号：US20220399333A1

公开(公告)日：2022-12-15

申请号：US17346990

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Mohit K. HARAN ,  Mohammad HASAN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: Integrated circuit structures having metal gates with reduced aspect ratio cuts, and methods of fabricating integrated circuit structures having metal gates with reduced aspect ratio cuts, are described. For example, an integrated circuit structure includes a sub-fin having a portion protruding above a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric structure is laterally spaced apart from the plurality of horizontally stacked nanowires. A dielectric gate plug is landed on the dielectric structure.

公开(公告)号：US20220392808A1

公开(公告)日：2022-12-08

申请号：US17339160

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohammad HASAN ,  William HSU ,  Biswajeet GUHA ,  Charles H. WALLACE ,  Tahir GHANI ,  Sean PURSEL ,  Tsuan-Chung CHANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Gate aligned fin cut for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment. A first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment. A second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment. An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.

公开(公告)号：US20220254893A1

公开(公告)日：2022-08-11

申请号：US17733834

申请日：2022-04-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Swaminathan SIVAKUMAR

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: Self-aligned gate endcap architectures with gate-all-around devices having epitaxial source or drain structures are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. A gate endcap isolation structure is between the first and second gate stacks, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires and have an uppermost surface below an uppermost surface of the gate endcap isolation structure. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires and have an uppermost surface below the uppermost surface of the gate endcap isolation structure.

公开(公告)号：US20220093592A1

公开(公告)日：2022-03-24

申请号：US17030212

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Michael K. HARPER ,  William HSU ,  Biswajeet GUHA ,  Tahir GHANI ,  Niels ZUSSSBLATT ,  Jeffrey Miles TAN ,  Benjamin KRIEGEL ,  Mohit K. HARAN ,  Reken PATEL ,  Oleg GOLONZKA ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L27/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  G11C5/06

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

公开(公告)号：US20210202534A1

公开(公告)日：2021-07-01

申请号：US16727370

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Chung-Hsun LIN ,  Biswajeet GUHA ,  William HSU ,  Stephen CEA ,  Tahir GHANI

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/84 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.

公开(公告)号：US20200091144A1

公开(公告)日：2020-03-19

申请号：US16134719

申请日：2018-09-18

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Swaminathan SIVAKUMAR

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423

Abstract: Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

公开(公告)号：US20200006491A1

公开(公告)日：2020-01-02

申请号：US16022508

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Biswajeet GUHA ,  Anupama BOWONDER ,  Tahir GHANI

IPC: H01L29/165 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/417 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a relatively high germanium content are described. In an example, an integrated circuit structure includes a fin including a semiconductor material. A gate stack is over an upper fin portion of the fin. A first epitaxial source or drain structure is embedded in the fin at a first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at a second side of the gate stack. The first and second epitaxial source or drain structures include silicon and germanium and have a same or greater atomic concentration of germanium than the fin.

公开(公告)号：US20190019891A1

公开(公告)日：2019-01-17

申请号：US16070262

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Anand S. MURTHY ,  Karthik JAMBUNATHAN ,  Chandra S. MOHAPATRA ,  Hei KAM ,  Nabil G. MISTKAWI ,  Jun Sung KANG ,  Biswajeet GUHA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/423

Abstract: A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.