公开(公告)号：US20210125992A1

公开(公告)日：2021-04-29

申请号：US16645362

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Travis LAJOIE ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Shem O. OGADHOH ,  Yih WANG ,  Bernhard SELL ,  Allen GARDINER ,  Blake LIN ,  Juan G. ALZATE VINASCO ,  Pei-Hua WANG ,  Chieh-Jen KU ,  Abhishek A. SHARMA

IPC: H01L27/108 ,  H01L27/12

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.

公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

Applicant: Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC: H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20210050455A1

公开(公告)日：2021-02-18

申请号：US17074251

申请日：2020-10-19

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Kent E. MILLARD ,  Marc C. FRENCH ,  Ashish AGRAWAL ,  Benjamin CHU-KUNG ,  Ryan E. ARCH

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/24 ,  H01L29/40 ,  H01L29/49

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20200312971A1

公开(公告)日：2020-10-01

申请号：US16369517

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Ashish PENUMATCHA ,  Seung Hoon SUNG ,  Scott CLENDENNING ,  Uygar AVCI ,  Ian A. YOUNG ,  Jack T. KAVALIEROS

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a FinFET transistor on the substrate. The FinFET transistor includes a fin structure having a channel area, a source area, and a drain area. The FinFET transistor further includes a gate dielectric area between spacers above the channel area of the fin structure and below a top surface of the spacers; spacers above the fin structure and around the gate dielectric area; and a metal gate conformally covering and in direct contact with sidewalls of the spacers. The gate dielectric area has a curved surface. The metal gate is in direct contact with the curved surface of the gate dielectric area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200219979A1

公开(公告)日：2020-07-09

申请号：US16240369

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Aaron LILAK ,  Patrick MORROW ,  Anh PHAN ,  Cheng-Ying HUANG ,  Ehren MANNEBACH

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

公开(公告)号：US20200083354A1

公开(公告)日：2020-03-12

申请号：US16465763

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Dipanjan BASU ,  Ashish AGRAWAL ,  Van H. LE ,  Benjamin CHU-KUNG ,  Harold W. KENNEL ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200066855A1

公开(公告)日：2020-02-27

申请号：US16074373

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Glenn A. GLASS ,  Harold W. KENNEL ,  Anand S. MURTHY ,  Willy RACHMADY ,  Gilbert DEWEY ,  Sean T. MA ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/201

Abstract: An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material.

公开(公告)号：US20200066515A1

公开(公告)日：2020-02-27

申请号：US16303125

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Willy RACHMADY ,  Marc C. FRENCH ,  Seung Hoon SUNG ,  Jack T. KAVALIEROS ,  Matthew V. METZ ,  Ashish AGRAWAL

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.

公开(公告)号：US20190393223A1

公开(公告)日：2019-12-26

申请号：US16480948

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Van H. LE ,  Gilbert William DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Yih WANG ,  Shriram SHIVARAMAN

IPC: H01L27/108 ,  H01L27/13 ,  G11C11/4096 ,  G11C11/408 ,  H01L29/786 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40 ,  H01L21/311 ,  H01L49/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/24 ,  H01L29/22

Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.

公开(公告)号：US20190341481A1

公开(公告)日：2019-11-07

申请号：US16309049

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Willy RACHMADY ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Sean T. MA ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: An apparatus is described. The apparatus includes a FINFET transistor. The FINFET transistor comprises a tapered subfin structure having a sidewall surface area that is large enough to induce aspect ratio trapping of lattice defects along sidewalls of the subfin structure so that the defects are substantially prevented from reaching said FINFET transistor's channel.