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    Binaural recording for processing audio signals to enable alerts
    81.
    发明授权
    Binaural recording for processing audio signals to enable alerts 有权

    公开(公告)号：US11095985B2

    公开(公告)日：2021-08-17

    申请号：US16862208

    申请日：2020-04-29

    Applicant: Intel Corporation

    Inventor： Rajesh Poornachandran ,  David Gottardo ,  Swarnendu Kar ,  Saurabh Dadu ,  Mark MacDonald

    IPC: H04R1/10 ,  H04R3/00 ,  H04R5/04 ,  G10L25/51 ,  G10L25/30 ,  H04S7/00

    Abstract: An example apparatus includes: a first earpiece to be positioned proximate a first ear of a user and including: a first microphone to transduce ambient sound external to the first earpiece into a first ambient audio signal, the ambient sound including sound indicative of a potential danger; and a first speaker to transduce a first input audio signal into music and the first ambient audio signal into the sound indicative of the potential danger; and a second earpiece to be positioned proximate a second ear of the user and including: a second microphone to transduce the ambient sound external to the second earpiece into a second ambient audio signal, the ambient sound including the sound indicative of the potential danger; and a second speaker to transduce a second input audio signal into the music and the second ambient audio signal into the sound indicative of the potential danger.

    APPLICATION AWARE GRACEFUL OVER CURRENT PROTECTION FOR MULTI-SOCKET PLATFORMS
    83.
    发明申请
    APPLICATION AWARE GRACEFUL OVER CURRENT PROTECTION FOR MULTI-SOCKET PLATFORMS 有权

    公开(公告)号：US20210141665A1

    公开(公告)日：2021-05-13

    申请号：US17122693

    申请日：2020-12-15

    Applicant: Intel Corporation

    Inventor： Rajesh Poornachandran ,  Rajendrakumar Chinnaiyan ,  Vincent Zimmer ,  Ravikiran Chukka

    IPC: G06F9/48 ,  G06F1/30 ,  G06F9/455 ,  H02H1/00 ,  G05F1/625

    Abstract: Systems, apparatuses and methods may provide for technology that detects an over current condition associated with a voltage regulator in a computing system, identifies a configurable over current protection policy associated with the voltage regulator, and automatically takes a protective action based on the configurable over current protection policy. In one example, the protective action includes one or more of a frequency throttle of a processor coupled to the voltage regulator in isolation from one or more additional processors in the computing system, a deactivation of the processor in isolation from the one or more additional processors, an issuance of a virtual machine monitor notification, an issuance of a data center fleet manager notification, or an initiation of a migration of a workload from the processor to at least one of the additional processor(s).

    METHODS AND ARRANGEMENTS TO IDENTIFY ACTIVATION PROFILE CONTEXT IN TRAINING DATA
    85.
    发明申请
    METHODS AND ARRANGEMENTS TO IDENTIFY ACTIVATION PROFILE CONTEXT IN TRAINING DATA 审中-公开

    公开(公告)号：US20200302301A1

    公开(公告)日：2020-09-24

    申请号：US16894535

    申请日：2020-06-05

    Applicant: Intel Corporation

    Inventor： Glen J. Anderson ,  Rajesh Poornachandran ,  Ignacio Alvarez ,  Giuseppe Raffa ,  Jill Boyce ,  Ankur Agrawal ,  Kshitij Doshi

    IPC: G06N3/08 ,  G06N3/04

    Abstract: Logic may determine a specific performance of a neural network based on an event and may present the specific performance to provide a user with an explanation of the inference by a machine learning model such as a neural network. Logic may determine a first activation profile associated with the event, the first activation profile based on activation of nodes in one or more layers of the neural network during inference to generate an output. Logic may correlate the first activation profile against a second activation profile associated with a first training sample of training data. Logic may determine that the first training sample is associated with the event based on the correlation. Logic may output an indicator to identify the first training sample as being associated with the event.

    Techniques for coordinating device boot security
    86.
    发明授权
    Techniques for coordinating device boot security 有权

    公开(公告)号：US10747884B2

    公开(公告)日：2020-08-18

    申请号：US15778980

    申请日：2015-12-24

    Applicant: INTEL CORPORATION

    Inventor： Jiewen Yao ,  Vincent J. Zimmer ,  Wei Li ,  Rajesh Poornachandran ,  Giri P. Mudusuru

    IPC: G06F21/57 ,  G06F21/44 ,  G06F21/53 ,  G06F9/4401 ,  G06F9/54

    Abstract: Techniques for providing and maintaining protection of firmware routines that form part of a chain of trust through successive processing environments. An apparatus may include a first processor component (550); a volatile storage (562) coupled to the first processor component; an enclave component to, in a pre-OS operating environment, generate a secure enclave within a portion of the volatile storage to restrict access to a secured firmware loaded into the secure enclave; a first firmware driver (646) to, in the pre-OS operating environment, provide a first API to enable unsecured firmware to call a support routine of the secured firmware from outside the secure enclave; and a second firmware driver (647) to, in an OS operating environment that replaces the pre-OS operating environment, provide a second API to enable an OS of the OS operating environment to call the support routine from outside the secure enclave.

    Dynamic reconfiguration and management of memory using field programmable gate arrays
    87.
    发明授权
    Dynamic reconfiguration and management of memory using field programmable gate arrays 有权

    公开(公告)号：US10649918B2

    公开(公告)日：2020-05-12

    申请号：US15718640

    申请日：2017-09-28

    Applicant: INTEL CORPORATION

    Inventor： Rajesh Poornachandran ,  Vincent J. Zimmer ,  Ned M. Smith ,  Nadhiya Chandramohan

    IPC: G06F12/14 ,  G06F9/4401 ,  G06F9/455 ,  G06F21/57 ,  G06F12/06 ,  G06F11/10 ,  G11C29/52 ,  G06F21/53 ,  G06N20/00 ,  G11C29/02

    Abstract: Techniques are provided for managing memory hot-add to a computing platform. A system implementing the techniques according to an embodiment includes a Field Programmable Gate Array (FPGA) memory controller (FMC) including a Memory Reference Code (MRC) Register Transfer Level (RTL) module to perform training of a memory module in response to receiving a memory hot-add event notification associated with the memory module. The MRC training includes memory timing adjustment based on configuration policies. The system also includes a management controller circuit to communicate with a remote administration server over a secure out-of-band network channel. The communication includes the configuration policies to be applied by the FMC circuit to the memory module. The FMC circuit further includes an analytics RTL module to perform bandwidth analysis and traffic prioritization, an encryption RTL module to perform encryption, and an error correction code (ECC) RTL module in conjunction with the configuration policies.

    Technologies for secure boot provisioning and management of field-programmable gate array images
    90.
    发明授权
    Technologies for secure boot provisioning and management of field-programmable gate array images 有权

    公开(公告)号：US10528765B2

    公开(公告)日：2020-01-07

    申请号：US15267322

    申请日：2016-09-16

    Applicant: Intel Corporation

    Inventor： Ned M. Smith ,  Rajesh Poornachandran

    IPC: G06F21/44 ,  G06F21/64 ,  G06F9/4401 ,  G06F21/57

    Abstract: Technologies for configuring a FPGA include a computing device having a processor and an FPGA. The computing device starts a secure boot process to establish a chain of trust that includes a trusted execution environment. The trusted execution environment loads an FPGA hash from an FPGA manifest stored in secure storage, and a platform trusted execution environment determines whether the FPGA hash is allowed for launch. To determine if the FPGA hash is allowed for launch, the platform trusted execution environment may evaluate one or more launch policies from the FPGA manifest. If allowed, the trusted execution environment configures the FPGA with an FPGA image corresponding to the FPGA hash and verifies the FPGA image with the FPGA hash. The platform trusted execution environment may receive the FPGA hash from a user via a trusted I/O session or from a remote management server. Other embodiments are described and claimed.

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