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公开(公告)号:US10649918B2
公开(公告)日:2020-05-12
申请号:US15718640
申请日:2017-09-28
Applicant: INTEL CORPORATION
Inventor: Rajesh Poornachandran , Vincent J. Zimmer , Ned M. Smith , Nadhiya Chandramohan
IPC: G06F12/14 , G06F9/4401 , G06F9/455 , G06F21/57 , G06F12/06 , G06F11/10 , G11C29/52 , G06F21/53 , G06N20/00 , G11C29/02
Abstract: Techniques are provided for managing memory hot-add to a computing platform. A system implementing the techniques according to an embodiment includes a Field Programmable Gate Array (FPGA) memory controller (FMC) including a Memory Reference Code (MRC) Register Transfer Level (RTL) module to perform training of a memory module in response to receiving a memory hot-add event notification associated with the memory module. The MRC training includes memory timing adjustment based on configuration policies. The system also includes a management controller circuit to communicate with a remote administration server over a secure out-of-band network channel. The communication includes the configuration policies to be applied by the FMC circuit to the memory module. The FMC circuit further includes an analytics RTL module to perform bandwidth analysis and traffic prioritization, an encryption RTL module to perform encryption, and an error correction code (ECC) RTL module in conjunction with the configuration policies.
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公开(公告)号:US20190095352A1
公开(公告)日:2019-03-28
申请号:US15718640
申请日:2017-09-28
Applicant: INTEL CORPORATION
Inventor: Rajesh Poornachandran , Vincent J. Zimmer , Ned M. Smith , Nadhiya Chandramohan
IPC: G06F12/14 , G06N99/00 , G06F9/44 , G06F9/455 , G06F21/57 , G06F21/53 , G06F12/06 , G06F11/10 , G11C29/52
Abstract: Techniques are provided for managing memory hot-add to a computing platform. A system implementing the techniques according to an embodiment includes a Field Programmable Gate Array (FPGA) memory controller (FMC) including a Memory Reference Code (MRC) Register Transfer Level (RTL) module to perform training of a memory module in response to receiving a memory hot-add event notification associated with the memory module. The MRC training includes memory timing adjustment based on configuration policies. The system also includes a management controller circuit to communicate with a remote administration server over a secure out-of-band network channel. The communication includes the configuration policies to be applied by the FMC circuit to the memory module. The FMC circuit further includes an analytics RTL module to perform bandwidth analysis and traffic prioritization, an encryption RTL module to perform encryption, and an error correction code (ECC) RTL module in conjunction with the configuration policies.
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公开(公告)号:US10546156B2
公开(公告)日:2020-01-28
申请号:US15410123
申请日:2017-01-19
Applicant: INTEL CORPORATION
Inventor: Rajesh Poornachandran , Vincent Zimmer , Ned Smith , Nadhiya Chandramohan
Abstract: MRC training can include providing a hot add notification to a UEFI BIOS FW, receiving, at an MRC agent of the FIMC and from the UEFI BIOS FW, the MRC training request, and performing, at the MRC agent in response to the MRC training request, an MRC training independent of an SMM associated with the apparatus.
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公开(公告)号:US10768863B2
公开(公告)日:2020-09-08
申请号:US15476693
申请日:2017-03-31
Applicant: INTEL CORPORATION
Inventor: Rajesh Poornachandran , Vincent J. Zimmer , Ned M. Smith , Nadhiya Chandramohan
Abstract: Techniques related to preventing unauthorized access to a computing device are disclosed. The techniques include a machine-readable medium, on which are stored instructions, comprising instructions that when executed cause a device to identify a host hardware configuration, obtain a policy based on the host hardware configuration, monitor two or more memory transactions based on the policy, identify, based on the memory transactions, a memory transaction pattern, wherein the memory transaction pattern is associated with an attempt to obtain unauthorized access to the device, and take one or more actions to interfere with attempts to obtain unauthorized access to the device based on the policy.
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