公开(公告)号：US11455107B2

公开(公告)日：2022-09-27

申请号：US16666351

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Suresh Rajgopal ,  Ling Wang ,  Yue Wei ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A method is implemented for a memory sub-system that detects a sequential write pattern in a write sequence for a memory device in a set of commands received from a host, detects current bandwidth utilization deviating from a write bandwidth utilization performance target, in response to detecting the sequential write pattern, and adjusts write bandwidth utilization to conform to the write bandwidth utilization target, in response to detecting the current bandwidth utilization deviating from the write bandwidth utilization performance target.

公开(公告)号：US11436078B2

公开(公告)日：2022-09-06

申请号：US17228425

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Xiangang Luo ,  Jianmin Huang ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam

IPC: G06F11/10 ,  G11C7/10 ,  G11C11/419 ,  G06F12/02

Abstract: Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.

公开(公告)号：US20220276784A1

公开(公告)日：2022-09-01

申请号：US17744563

申请日：2022-05-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Shane Nowell ,  Michael Sheperek

IPC: G06F3/06

Abstract: A system can include a memory device and a processing device to perform operations that include performing, at a first frequency, a calibration scan, where the calibration scan includes calibrating block family-to-bin associations for one or more younger voltage bins based on first measurement data determined by the calibration scan, and calibrating block family-to-bin associations for one or more older voltage bins based on second measurement data provided by a media management scan, where the media management scan is performed at a second frequency, such that the second frequency is lower than the first frequency, each of the younger voltage bins satisfies a first age threshold criterion, and each of the older voltage bins satisfies a second age threshold criterion.

公开(公告)号：US11429309B2

公开(公告)日：2022-08-30

申请号：US16930064

申请日：2020-07-15

Applicant: Micron Technology, Inc.

Inventor： Mustafa N Kaynak ,  Sampath K Ratnam ,  Zixiang Loh ,  Nagendra Prasad Ganesh Rao ,  Larry K Koudele ,  Vamsi Pavan Rayaprolu ,  Patrick R Khayat ,  Shane Nowell

IPC: G06F3/06 ,  G06F11/07

Abstract: A processing device, operatively coupled with a memory device, is configured to identify a temperature related to a memory device of a plurality of memory devices; to determine, whether the temperature satisfies a threshold temperature condition; responsive to detecting that the temperature related to the memory device satisfies the threshold temperature condition, to identify an entry associated with the memory device from a plurality of entries in a data structure, wherein each entry of the plurality of entries corresponds to one of the plurality of memory devices; to determine a parameter value associated with the memory device from the entry, wherein the parameter value is for a programming operation to store data at the memory device; to adjust the parameter value associated with the memory device to generate an adjusted parameter value; and to store the adjusted parameter value in the entry of the data structure.

公开(公告)号：US11416388B2

公开(公告)日：2022-08-16

申请号：US17027895

申请日：2020-09-22

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Vamsi Pavan Rayaprolu ,  Karl D. Schuh ,  Jiangang Wu ,  Gil Golov

IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/0873 ,  G06F11/30 ,  G06F12/0811

Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can determine a data rate from a first sensor and a data rate from a second sensor. The processing device can write a first set of data received from the first sensor at a first logical block address (LBA) in the memory device. The processing device can write a second set of data received from the second sensor and subsequent to the first set of data at a second LBA in the memory device. The processing device can remap the first LBA and the second LBA to be logically sequential LBAs. The second LBA can be associated with an offset from the first LBA and the offset can correspond to a data rate of the first sensor.

公开(公告)号：US20220199179A1

公开(公告)日：2022-06-23

申请号：US17127012

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Sampath K. Ratnam ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Gary F. Besinga ,  Michael G. Miller ,  Tawalin Opastrakoon

IPC: G11C29/10

Abstract: In one embodiment, a system maintains metadata associating each block of a plurality of blocks of the memory device with a corresponding frequency access group, where each frequency access group is associated with a corresponding scan frequency. The system determines that a first predetermined time period has elapsed since a last scan operation performed with respect to one or more blocks of the memory device, where the first predetermined time period specifies a first scan frequency. The system selects, based on the metadata, at least one block from a first frequency access group associated with the first scan frequency. The system performs a scan operation with respect to the selected block.

公开(公告)号：US20220188223A1

公开(公告)日：2022-06-16

申请号：US17536928

申请日：2021-11-29

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  Vamsi Pavan Rayaprolu ,  Jiangang Wu ,  Kishore K. Muchherla

IPC: G06F12/02 ,  G06F12/0882 ,  G06F3/06

Abstract: A system includes a memory device and a processing device communicatively coupled to the memory device. The processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. The processing device is further to track a sequence in which the number of groups of memory cells were written with the data. In response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.

公开(公告)号：US20220188034A1

公开(公告)日：2022-06-16

申请号：US17552237

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  Jiangang Wu ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can assign each of a plurality of superblocks to one of a plurality of groups. The processing device can monitor an order that each of the groups have been written to. The processing device can write data to a first block of a first superblock of a first of the plurality of groups.

公开(公告)号：US20220179577A1

公开(公告)日：2022-06-09

申请号：US17681075

申请日：2022-02-25

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Harish R. Singidi ,  Gianni S. Alsasua

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/34

Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.

公开(公告)号：US11354037B2

公开(公告)日：2022-06-07

申请号：US16947713

申请日：2020-08-13

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Harish R. Singidi ,  Ashutosh Malshe ,  Kishore Kumar Muchherla

IPC: G06F3/06

Abstract: A system includes a memory component and a processing device to determine an amount of data stored at a region of a memory component and determine, based on the amount of data stored in the region of the memory component. The processing device determines a frequency to perform an operation on one or more memory cells of the region of the memory component. The processing device performs the operation on the one or more memory cells at the frequency to maintain the one or more memory cells of the region of the memory component in a first state associated with a first error rate for data stored at the one or more memory cells. The first error rate is less than a second error rate associated with a second state of the one or more memory cells.