公开(公告)号：US20210390016A1

公开(公告)日：2021-12-16

申请号：US17461918

申请日：2021-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harish R. Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F11/10 ,  G06F11/07 ,  G06F12/0882 ,  G06F11/30 ,  G06F12/02

Abstract: A processing device, operatively coupled with the memory device, is configured to determine a first error rate associated a first set of pages of a plurality of pages of a data unit of a memory device, and a second error rate associated with a second set of pages of the plurality of pages of the data unit, determine a first pattern of error rate change for the data unit based on the first error rate and the second error rate, and responsive to determining that the first pattern of error rate change corresponds to a predetermined second pattern of error rate change, perform an action pertaining to defect remediation with respect to the data unit.

公开(公告)号：US11194646B2

公开(公告)日：2021-12-07

申请号：US16702399

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Harish R. Singidi ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Qisong Lin ,  Kishore Kumar Muchherla

IPC: G06F11/07 ,  G06F11/10 ,  G06F11/30 ,  G06F3/06

Abstract: Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.

公开(公告)号：US11175979B2

公开(公告)日：2021-11-16

申请号：US16533328

申请日：2019-08-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Harish R. Singidi ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Xiangang Luo

IPC: G06F11/07

Abstract: A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.

公开(公告)号：US11158392B2

公开(公告)日：2021-10-26

申请号：US16412879

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G11C16/34

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

公开(公告)号：US11157400B2

公开(公告)日：2021-10-26

申请号：US16737662

申请日：2020-01-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Sampath K. Ratnam ,  Ashutosh Malshe

IPC: G06F3/06 ,  G06F12/02 ,  G06F11/30 ,  G06F12/0811 ,  G06F12/0871

Abstract: A garbage collection operation can be performed on one or more data blocks of a memory sub-system, where data is stored at the one or more data blocks using a first write mode. In response to determining that the garbage collection operation satisfies a performance condition, a determination is made as to whether a data block of a cache area of the memory sub-system satisfies an endurance condition, where data is stored at the data block of the cache area using a second write mode. A write mode for the data block of the cache area is changed from the second write mode to the first write mode responsive to determining that the data block satisfies the endurance condition. The data block of the cache area is then used in the garbage collection operation.

公开(公告)号：US11106577B2

公开(公告)日：2021-08-31

申请号：US16175005

申请日：2018-10-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Sean Feeley ,  Sampath K. Ratnam ,  Ashutosh Malshe ,  Christopher S. Hale

IPC: G06F12/128 ,  G06F12/02 ,  G06F12/0897

Abstract: An amount of valid data for each data block of multiple data blocks stored at a first memory is determined. An operation to write valid data of a particular data block from the first memory to a second memory is performed based on the amount of valid data for each data block. A determination is made that a threshold condition associated with when valid data of the data blocks was written to the first memory has been satisfied. In response to determining that the threshold condition has been satisfied, the operation to write valid data of the data blocks from the first memory to the second memory is performed based on when the valid data was written to the first memory.

公开(公告)号：US20210241823A1

公开(公告)日：2021-08-05

申请号：US17238846

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, JR.

IPC: G11C11/406 ,  G06F13/16 ,  G11C7/04

Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

公开(公告)号：US20210191858A1

公开(公告)日：2021-06-24

申请号：US17196934

申请日：2021-03-09

Applicant: Micron Technology, Inc.

Inventor： Yun Li ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam

IPC: G06F12/02 ,  G06F12/0891

Abstract: Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.

公开(公告)号：US10998034B2

公开(公告)日：2021-05-04

申请号：US17017201

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, Jr.

IPC: G11C7/04 ,  G11C11/406 ,  G06F13/16

Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

公开(公告)号：US20210117318A1

公开(公告)日：2021-04-22

申请号：US17247805

申请日：2020-12-23

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Ashutosh Malshe ,  Peter Sean Feeley

IPC: G06F12/02

Abstract: A processing device in a memory system determines a rate at which an amount of valid data is decreasing on a first block of the memory device and determines whether the rate at which the amount of valid data is decreasing on the first block satisfies a threshold criterion. Responsive to the rate at which the amount of valid data is decreasing on the first block satisfying the threshold criterion, the processing device performs a media management operation on the first block of the memory device.