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    Drive strength calibration for multi-level signaling
    81.
    发明授权
    Drive strength calibration for multi-level signaling 有权

    公开(公告)号：US12148502B2

    公开(公告)日：2024-11-19

    申请号：US18202584

    申请日：2023-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Peter Mayer ,  Wolfgang Anton Spirkl ,  Michael Dieter Richter ,  Martin Brox ,  Thomas Hein

    IPC: G11C7/22 ,  G11C5/14 ,  G11C7/10 ,  G11C11/22 ,  G11C11/56

    Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

    Adapting channel current
    82.
    发明授权
    Adapting channel current 有权

    公开(公告)号：US12081331B2

    公开(公告)日：2024-09-03

    申请号：US16579275

    申请日：2019-09-23

    Applicant: Micron Technology, Inc.

    Inventor： Martin Brox ,  Peter Mayer ,  Michael Dieter Richter ,  Thomas Hein ,  Wolfgang Anton Spirkl

    IPC: H04L1/00 ,  G11C7/10 ,  G11C11/22 ,  G11C11/56 ,  H04L25/02 ,  H04L25/49

    CPC classification number: H04L1/0032 ,  G11C7/1057 ,  G11C11/56 ,  H04L1/0014 ,  H04L1/0046

    Abstract: Methods, systems, and devices for operating memory cell(s) using adapting the current on a channel are described. A current on a channel may be adapted during a transition period between signaling a first logic value over the channel and signaling a second (e.g. subsequent) logic value over the channel. Adapting the current may include increasing or decreasing the current on the channel during the transition period. The degree of adaptation may be based on a difference between the first logic value and the subsequent logic value. In some cases, a logic circuit may be configured to determine a difference between the first and subsequent logic value. The logic circuit may be further configured to communicate the difference to an adaptive driver. And the adaptive driver may adapt a current of the channel based on the communicated difference.

    Error information signaling for memory
    83.
    发明授权
    Error information signaling for memory 有权

    公开(公告)号：US11782608B1

    公开(公告)日：2023-10-10

    申请号：US17749966

    申请日：2022-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Michael Dieter Richter ,  Thomas Hein ,  Casto Salobrena Garcia

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0625 ,  G06F3/0655

    Abstract: Methods, systems, and devices for error information signaling for memory are described. A memory device may perform an error detection procedure while in a power-saving mode. Upon detecting an error, the memory device may indicate the error to a host device. In response to indicating the error, the memory device may receive a command to exit the power-saving mode. The memory device may comply with the command and exit the power-saving mode by enabling one or more interfaces of the memory device. The memory device may receive a request for error information over the one or more interfaces and, in response to the request, may transmit the error information to the host device.

    DATA SCRAMBLING FOR REPEAT OPERATIONS
    86.
    发明公开
    DATA SCRAMBLING FOR REPEAT OPERATIONS 审中-公开

    公开(公告)号：US20230198652A1

    公开(公告)日：2023-06-22

    申请号：US18059228

    申请日：2022-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Martin Brox ,  Thomas Hein

    IPC: H04J13/10

    CPC classification number: H04J13/10

    Abstract: Methods, systems, and devices for data scrambling for repeat operations are described. A first device may communicate a data set to a second device as a first set of bits. The first device may use a first scrambling code to scramble the first set of bits and the second device may use a first descrambling code to descramble the first set of bits. Upon determining that the first set of bits was received by the second device with an error, the first device may communicate the data set to the second device as a second set of bits. The first device may use a second scrambling code to scramble the second set of bits and the second device may use a second descrambling code to descramble the second set of bits

    LINK EVALUATION FOR A MEMORY DEVICE
    87.
    发明公开
    LINK EVALUATION FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230197181A1

    公开(公告)日：2023-06-22

    申请号：US18112830

    申请日：2023-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Markus Balb ,  Thomas Hein ,  Heinz Hoenigschmid

    IPC: G11C29/44 ,  G11C29/38 ,  G11C29/12

    CPC classification number: G11C29/44 ,  G11C29/38 ,  G11C29/12005 ,  G11C2207/2254

    Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

    Method and apparatus for signal path biasing in a memory system
    88.
    发明授权
    Method and apparatus for signal path biasing in a memory system 有权

    公开(公告)号：US11609865B2

    公开(公告)日：2023-03-21

    申请号：US16849740

    申请日：2020-04-15

    Applicant: Micron Technology, Inc.

    Inventor： Wolfgang Anton Spirkl ,  Thomas Hein ,  Martin Brox ,  Peter Mayer ,  Michael Dieter Richter

    IPC: G06F13/16 ,  G11C11/4093 ,  G06F13/12 ,  G11C11/22 ,  G11C11/4091

    Abstract: Methods, systems, and devices for signal path biasing in an electronic system (e.g., a memory system) are described. In one example, a memory device, a host device, or both may be configured to bias a signal path, between an idle state and an information transfer or between an information transfer and an idle state, to an intermediate or mid-bias voltage level, which may reduce signal interference associated with such transitions. In various examples, the described biasing to a voltage, such as a mid-bias voltage, may be associated with an access command or other command for information to be communicated between devices of the electronic system, such as a command for information to be communicated between a memory device and a host device.

    BIT AND SIGNAL LEVEL MAPPING
    90.
    发明申请
    BIT AND SIGNAL LEVEL MAPPING 有权

    公开(公告)号：US20220245026A1

    公开(公告)日：2022-08-04

    申请号：US17726418

    申请日：2022-04-21

    Applicant: Micron Technology, Inc.

    Inventor： Stefan Dietrich ,  Martin Brox ,  Michael Dieter Richter ,  Thomas Hein ,  Ronny Schneider ,  Natalija Jovanovic

    IPC: G06F11/10

    Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations may generate one or more bits of CRC output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process may be configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

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