公开(公告)号：US09196500B2

公开(公告)日：2015-11-24

申请号：US13859720

申请日：2013-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Chien-Ting Lin

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/3086 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/66795

Abstract: A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.

Abstract translation: 一种用于制造半导体结构的方法，包括提供具有多个心轴图案和多个虚拟图案的基板，同时在心轴图案的侧壁上形成多个第一间隔件，在虚设图案的侧壁上形成多个第二间隔件，以及 移除第二间隔件和心轴图案以在基底上形成多个间隔图案。

公开(公告)号：US20150332976A1

公开(公告)日：2015-11-19

申请号：US14811814

申请日：2015-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin ,  Chien-Ming Lai ,  Chi-Mao Hsu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32115 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L29/7833

Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括以下步骤。 提供了具有形成在其上的第一半导体器件和第二半导体器件的衬底。 第一半导体器件包括第一栅极沟槽，第二半导体器件包括第二栅极沟槽。 在第一栅极沟槽和第二栅极沟槽中形成第一功函数金属层。 第一功函数金属层的一部分从第二栅极沟槽去除。 在第一栅极沟槽和第二栅极沟槽中形成第二功函数金属层。 第二功函数金属层和第一功函数金属层包括相同的金属材料。 在第一栅极沟槽和第二栅极沟槽中依次形成第三功函数金属层和间隙填充金属层。

公开(公告)号：US09190497B2

公开(公告)日：2015-11-17

申请号：US14630666

申请日：2015-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Hong ,  Po-Chao Tsao

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/6653

Abstract: A fabrication method of a semiconductor device includes the following steps. First, sacrificial patterns are formed on a substrate and a space is formed on the sidewalls of each sacrificial pattern. Then, the sacrificial patterns are removed and patterns of the spacers are transferred into the substrate to form a fin structure. The fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. Subsequently, a gate structure, source/drain structures, and an electrical connecting structure are formed sequentially on the substrate. The gate structure overlaps portions of the horizontal fin structure. The source/drain structures are respectively on each side of the gate structure. The electrical connecting structure directly covers the horizontal fin structure and the vertical fin structure.

Abstract translation: 半导体器件的制造方法包括以下步骤。 首先，牺牲图案形成在基板上，并且在每个牺牲图案的侧壁上形成空间。 然后，去除牺牲图案，并将间隔物的图案转移到基板中以形成翅片结构。 翅片结构包括沿着第一方向延伸的水平翅片结构和沿着第二方向延伸的垂直翅片结构。 随后，在衬底上依次形成栅极结构，源极/漏极结构和电连接结构。 门结构与水平翅片结构的部分重叠。 源极/漏极结构分别位于栅极结构的每一侧。 电连接结构直接覆盖水平翅片结构和垂直翅片结构。

公开(公告)号：US20150200192A1

公开(公告)日：2015-07-16

申请号：US14153079

申请日：2014-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Yao-Hung Huang ,  Chien-Ting Lin ,  Ming-Te Wei

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L27/0922 ,  H01L21/02164 ,  H01L21/32115 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385

Abstract: The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench.

Abstract translation: 本发明提供一种半导体结构，包括其上设置有介电层的基板，限定在其上的第一器件区域和第二器件区域，设置在第一器件区域内的衬底中的至少一个第一沟槽，至少一个第二 沟槽和设置在第二器件区域内的衬底中的至少一个第三沟槽，设置在第二沟槽和第三沟槽中的功函数层，其中功函数层部分地覆盖第二沟槽的侧壁，并且完全覆盖 第三沟槽的侧壁和设置在第二沟槽和第三沟槽中的第一材料层，其中第一材料层覆盖设置在第二沟槽的部分侧壁上的功函数层，并且完全覆盖设置在第二沟槽上的功函数层 第三沟槽的侧壁。

公开(公告)号：US09064931B2

公开(公告)日：2015-06-23

申请号：US13649126

申请日：2012-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/485 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor structure including at least a contact plug. The structure includes a substrate, a transistor, a first ILD layer, a second ILD layer and a first contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor and levels with a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The first contact plug is disposed in the first ILD layer and the second ILD layer and includes a first trench portion and a first via portion, wherein a boundary of the first trench portion and a first via portion is higher than the top surface of the gate. The present invention further provides a method of making the same.

Abstract translation: 本发明提供至少包括接触插头的半导体结构。 该结构包括衬底，晶体管，第一ILD层，第二ILD层和第一接触插塞。 晶体管设置在衬底上并且包括栅极和源极/漏极区域。 第一ILD层设置在晶体管上并且与栅极的顶表面平齐。 第二ILD层设置在第一ILD层上。 第一接触插塞设置在第一ILD层和第二ILD层中，并且包括第一沟槽部分和第一通孔部分，其中第一沟槽部分和第一通孔部分的边界高于栅极的顶表面 。 本发明还提供了制备该方法的方法。

公开(公告)号：US20150147874A1

公开(公告)日：2015-05-28

申请号：US14088445

申请日：2013-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  I-Ming Tseng ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Po-Chao Tsao ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/8234 ,  H01L21/265

CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/3086 ,  H01L29/6681

Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.

Abstract translation: 本发明提供一种用于形成半导体结构的制造方法，其中首先设置基板，在基板上设置硬掩模，然后将硬掩模图案化以形成多个散热片硬掩模和多个虚拟 翅片硬掩模，然后进行图案转印处理，将翅片硬掩模和翅片硬掩模的图案转移到基板中，以形成多个翅片组和多个虚拟翅片。 每个假翅片设置在一个翅片组的端侧，并进行翅片切割处理，以去除每个假翅片。

公开(公告)号：US09013003B2

公开(公告)日：2015-04-21

申请号：US13728948

申请日：2012-12-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/336 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/823468 ,  H01L21/02068 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract translation: 半导体结构包括第一栅极和第二栅极，第一间隔物和第二间隔物，两个第一外延结构和两个第二外延结构。 第一栅极和第二栅极位于基板上。 第一间隔物和第二间隔物分别位于第一栅极和第二栅极旁边的衬底上。 第一外延结构和第二外延结构分别位于第一间隔物和第二间隔物旁边的衬底中，其中第一间隔物和第二间隔物具有不同的厚度，并且第一外延结构之间的间隔不同于 第二外延结构。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US09006804B2

公开(公告)日：2015-04-14

申请号：US13912173

申请日：2013-06-06

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Shih-Fang Tzou

IPC: H01L29/76 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28079 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Abstract translation: 本发明提供一种制造半导体器件的方法，包括以下步骤。 首先，在基板上形成第一层间电介质。 然后，在基板上形成栅电极，其中栅电极的周围被第一层间电介质包围。 之后，在栅电极上形成图案化掩模层，其中图案化掩模层的底表面与第一层间电介质的顶表面平齐。 然后形成第二层间电介质以覆盖图案化掩模层的顶表面和每个侧表面。 最后，在第一层间电介质和第二层间电介质中形成自对准接触结构。

公开(公告)号：US09006072B2

公开(公告)日：2015-04-14

申请号：US13802812

申请日：2013-03-14

Applicant: United Microelectronics Corp.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L29/665 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method of forming a metal silicide layer includes the following steps. At first, at least a gate structure, at least a source/drain region and a first dielectric layer are formed on a substrate, and the gate structure is aligned with the first dielectric layer. Subsequently, a cap layer covering the gate structure is formed, and the cap layer does not overlap the first dielectric layer and the source/drain region. Afterwards, the first dielectric layer is removed to expose the source/drain region, and a metal silicide layer totally covering the source/drain region is formed.

Abstract translation: 形成金属硅化物层的方法包括以下步骤。 首先，在基板上形成至少栅极结构，至少源极/漏极区域和第一电介质层，并且栅极结构与第一电介质层对准。 随后，形成覆盖栅极结构的覆盖层，并且覆盖层不与第一介电层和源极/漏极区重叠。 然后，去除第一电介质层以暴露源极/漏极区域，并且形成完全覆盖源极/漏极区域的金属硅化物层。

公开(公告)号：US20150052491A1

公开(公告)日：2015-02-19

申请号：US13968391

申请日：2013-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.

Abstract translation: 提供了一种用于生成布局图案的方法。 首先，将布局图案提供给计算机系统，并将其分为两个子图案和空白图案。 每个子图案具有简单整数比例的间距，并且空白图案在两个子图案之间。 然后，生成多个第一条纹图案和至少两个第二条纹图案。 第一条形图案的边缘与子图案的边缘对齐，并且第一条纹图案具有相等的间隔和宽度。 第二条纹图案的间距或宽度与第一条纹图案的间距或宽度不同。