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    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    81.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
    半导体结构及其工艺

    公开(公告)号：US20140159211A1

    公开(公告)日：2014-06-12

    申请号：US13710382

    申请日：2012-12-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chien-Liang Lin ,  Yu-Ren Wang ,  Ying-Wei Yen

    IPC: H01L21/02 ,  H01L21/441 ,  H01L29/06

    CPC classification number: H01L21/28185 ,  H01L21/02164 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/441 ,  H01L29/0603 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

    Abstract: A semiconductor structure includes a dielectric layer located on a substrate, wherein the dielectric layer includes nitrogen atoms, and the concentration of the nitrogen atoms in the dielectric layer is lower than 5% at a location wherein the distance between this location in the dielectric layer to the substrate is less than 20% of the thickness of the dielectric layer. Moreover, the present invention provides a semiconductor process including the following steps: a dielectric layer is formed on a substrate. Two annealing processes are performed in-situly on the dielectric layer, wherein the two annealing processes have different imported gases and different annealing temperatures.

    Abstract translation: 半导体结构包括位于基板上的电介质层，其中介电层包括氮原子，并且介电层中氮原子的浓度低于5％，其中介电层中该位置之间的距离与 基板的厚度小于电介质层厚度的20％。 此外，本发明提供一种包括以下步骤的半导体工艺：在基板上形成电介质层。 在电介质层上进行两个退火工艺，其中两个退火工艺具有不同的进口气体和不同的退火温度。

    High electron mobility transistor
    89.
    发明授权
    High electron mobility transistor 有权

    公开(公告)号：US11257939B2

    公开(公告)日：2022-02-22

    申请号：US16711451

    申请日：2019-12-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yen-Hsing Chen ,  Yu-Ming Hsu ,  Yu-Chi Wang ,  Tsung-Mu Yang ,  Yu-Ren Wang

    IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20

    Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.

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