公开(公告)号：US11749737B2

公开(公告)日：2023-09-05

申请号：US17500340

申请日：2021-10-13

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhongwang Sun ,  Zhong Zhang ,  Lei Liu ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L29/423 ,  H10B41/41 ,  H10B43/40 ,  H01L21/28

CPC classification number: H01L29/42372 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/41 ,  H10B43/40

Abstract: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

公开(公告)号：US11735543B2

公开(公告)日：2023-08-22

申请号：US17113557

申请日：2020-12-07

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lei Liu ,  Di Wang ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H10B12/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B12/0335 ,  H10B12/30 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1436

Abstract: A semiconductor device is provided. The semiconductor device includes a first wafer having an array transistor formed therein, and a second wafer having a capacitor structure formed therein. The semiconductor device also includes a bonding interface formed between the first wafer and second wafer that includes a plurality of bonding structures. The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell.

公开(公告)号：US11729971B2

公开(公告)日：2023-08-15

申请号：US17645102

申请日：2021-12-20

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang Xu ,  Zhiliang Xia ,  Ping Yan ,  Guangji Li ,  Zongliang Huo

IPC: H10B43/20 ,  H01L21/762 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

CPC classification number: H10B43/20 ,  H01L21/762 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

公开(公告)号：US20230209828A1

公开(公告)日：2023-06-29

申请号：US18118006

申请日：2023-03-06

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B41/40 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B41/40 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device comprises forming a channel structure extending vertically through a memory stack into a semiconductor layer on a substrate. The memory stack comprises interleaved stack conductive layers and stack dielectric layers. The method further comprises forming an insulating structure in an opening extending vertically through the memory stack and at a distance away from the channel structure, and comprising a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

公开(公告)号：US20230189521A1

公开(公告)日：2023-06-15

申请号：US17568630

申请日：2022-01-04

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Di Wang ,  Yan Gu ,  Zhiliang Xia ,  Wenxi Zhou ,  Zongliang Huo

IPC: H01L27/11578 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L27/11578 ,  H01L29/42344 ,  H01L29/4991 ,  H01L29/40117

Abstract: A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain-select gate (DSG) cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

公开(公告)号：US11665892B2

公开(公告)日：2023-05-30

申请号：US16881279

申请日：2020-05-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhongwang Sun ,  Zhong Zhang ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L27/11551 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11551 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11578

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first and second memory array structures. The bridge structure includes a lower wall portion and an upper staircase portion. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

公开(公告)号：US20230138205A1

公开(公告)日：2023-05-04

申请号：US17539784

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on all sides of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.

公开(公告)号：US20230133595A1

公开(公告)日：2023-05-04

申请号：US17539742

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: In certain aspects, a memory device includes a vertical transistor, a storage unit, a bit line, and a body line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and coupled to a second terminal. The second terminal is another one of the source and the drain. The body line is coupled to the channel portion of the semiconductor body.

公开(公告)号：US20230115194A1

公开(公告)日：2023-04-13

申请号：US18081172

申请日：2022-12-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L29/76

Abstract: A three-dimensional (3D) memory device is disclosed. The 3D memory device includes a memory stack, a semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack, and a source contact above the memory stack and in contact with the semiconductor layer. A semiconductor plug, in contact with the semiconductor layer, surrounds an end of one of the channel structures. The source contact is electrically connected with the one of the channel structures. At least a portion of the source contact is buried within the semiconductor layer.

公开(公告)号：US11600633B2

公开(公告)日：2023-03-07

申请号：US16862368

申请日：2020-04-29

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jianzhong Wu ,  Kun Zhang ,  Tingting Zhao ,  Rui Su ,  Zhongwang Sun ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, and a slit structure. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The slit structure includes a contact including a first contact portion and a second contact portion above the first contact portion and having a different material of the first contact portion. An upper end of the second contact portion of the slit structure is flush with an upper end of the channel local contact.