公开(公告)号：US07791330B2

公开(公告)日：2010-09-07

申请号：US12125730

申请日：2008-05-22

Applicant: David F. Heidel ,  Keith A. Jenkins

Inventor： David F. Heidel ,  Keith A. Jenkins

IPC: G01R13/02

CPC classification number: H04L1/205 ,  G01R29/26 ,  G01R31/3016 ,  G01R31/31709 ,  G01R31/31725

Abstract: An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, the circuit including a latch for latching and comparing the arrival time of the signal of interest to the reference clock, a clock counter in signal communication with the latch for counting the number of reference clock cycles received and latched, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, middle stages, and a last stage, and a voltage controller in signal communication with at least one of the middle stages of the delay chain for controlling the delay of the arrival time of the reference clock, wherein the voltage controller controls the first and last stages of the delay chain to retain a full voltage swing independent of the delay.

Abstract translation: 提供一种用于接收参考时钟和感兴趣信号的片上抖动测量电路和相应方法，该电路包括用于锁存和比较感兴趣信号到参考时钟的到达时间的锁存器，信号中的时钟计数器 与锁存器通信，用于对接收和锁存的参考时钟周期的数量进行计数;与参考时钟的信号通信的延迟链，用于改变参考时钟的到达时间;延迟链具有第一级，中间级和最后一位 以及与延迟链的至少一个中间级信号通信的电压控制器，用于控制参考时钟的到达时间的延迟，其中电压控制器控制延迟链的第一和最后阶段以保持 全电压摆幅独立于延时。

公开(公告)号：US07725809B2

公开(公告)日：2010-05-25

申请号：US11366125

申请日：2006-02-28

Applicant: Yoshihisa Adachi ,  Atsushi Etoh

Inventor： Yoshihisa Adachi ,  Atsushi Etoh

IPC: H03M13/03

CPC classification number: H04L1/205 ,  G11B7/1267 ,  G11B20/10009

Abstract: A Viterbi decoding circuit performs Viterbi decoding on the basis of a reproduced signal obtained by reading an optical disc. A decoded bit sequence is fed to a first specific pattern detection circuit and a first reverse pattern detection circuit. A path metric difference ΔM is fed to a reproduced signal evaluation circuit. The reproduced signal evaluation circuit extracts path metric differences for a specific pattern and a reverse pattern detected by the first specific pattern detection circuit and the first reverse pattern detection circuit and evaluates the reproduced signal on the basis of results. The evaluation uses not only the bit sequence for which the ideal SAM value is a minimum. The invention achieves accurate evaluation for reproduction.

Abstract translation: 维特比解码电路根据通过读取光盘获得的再现信号执行维特比解码。 解码的比特序列被馈送到第一特定模式检测电路和第一反向模式检测电路。 路径度量差Dgr; M馈送到再现信号评估电路。 再现信号评估电路提取由第一特定图案检测电路和第一反向图案检测电路检测到的特定图案和反向图案的路径度量差异，并且基于结果评估再现的信号。 评估不仅使用理想SAM值最小的比特序列。 本发明实现了对再现的准确评估。

公开(公告)号：US07711265B2

公开(公告)日：2010-05-04

申请号：US12274262

申请日：2008-11-19

Applicant: Brad L. Inman ,  Jan P. Peeters Weem ,  Rob J. Hensel

Inventor： Brad L. Inman ,  Jan P. Peeters Weem ,  Rob J. Hensel

IPC: H04B10/08 ,  H04B17/00

CPC classification number: H04L1/205 ,  H04J14/02

Abstract: In embodiments of the present invention, an optical device tester performs stressed eye testing on several optical receivers and transmission and dispersion penalty testing on optical transmitters at a variety of data rates wavelengths using single mode optical signals and multimode optical signals using a variety of supply voltages and temperatures.

Abstract translation: 在本发明的实施例中，光学设备测试仪使用单模光信号和使用多种电源电压的多模光信号，以多种数据速率波长在光发射机上对多个光接收机执行应力眼测试并进行传输和色散惩罚测试 和温度。

公开(公告)号：US20100061435A1

公开(公告)日：2010-03-11

申请号：US12584470

申请日：2009-09-04

Applicant: Barry Donald Ruberry Miles

Inventor： Barry Donald Ruberry Miles

IPC: H04B3/46

CPC classification number: G01R31/31726 ,  H04L1/205

Abstract: A jitter evaluation apparatus for receiving a digital test signal from which a clock signal is recovered, is shown. A clock recovery circuit (401) recovers a clock signal from the test signal and a synchronisation circuit generates a synchronised system clock signal from said recovered clock signal. A sinusoid generator (403) generates a sinusoid signal from the synchronised system clock signal and a sampling analog to digital converter (404) samples the sinusoid signal by the recovered clock signal to provide sinusoid samples further comprising: A numerically controlled oscillator (401) is configured to produce sine values and cosine values in response to receiving an input from the system clock signal and a first multiplier (412) is configured to produce a first product of the sinusoid samples and the sine values. In addition, a second multiplier is configured to produce a second product of the sinusoid samples and the cosine values. Furthermore, a co-ordinate rotation device (416) is configured to receive said first product via a first low pass filter (414) and to receive said second product via a second low pass filter (415) to produce an output indicative of jitter phase.

Abstract translation: 示出了用于接收从其恢复时钟信号的数字测试信号的抖动评估装置。 时钟恢复电路（401）从测试信号中恢复时钟信号，并且同步电路从所述恢复的时钟信号产生同步的系统时钟信号。 正弦波发生器（403）从同步的系统时钟信号产生正弦信号，并且采样模数转换器（404）通过恢复的时钟信号对正弦信号进行采样，以提供正弦曲线样本，进一步包括：数字振荡器（401） 被配置为响应于从系统时钟信号接收到输入而产生正弦值和余弦值，并且第一乘法器（412）被配置为产生正弦样本和正弦值的第一乘积。 另外，第二乘法器被配置为产生正弦曲线样本和余弦值的第二乘积。 此外，坐标旋转装置（416）被配置为经由第一低通滤波器（414）接收所述第一乘积并且经由第二低通滤波器（415）接收所述第二乘积以产生指示抖动相位的输出 。

公开(公告)号：US20100030503A1

公开(公告)日：2010-02-04

申请号：US12103689

申请日：2008-04-15

Applicant: Hayden C. Cranford, JR. ,  Fadi H. Gebara ,  Jeremy D. Schaub

Inventor： Hayden C. Cranford, JR. ,  Fadi H. Gebara ,  Jeremy D. Schaub

IPC: G06F19/00 ,  G06F17/18

CPC classification number: G01R31/31725 ,  G01R29/26 ,  G01R31/31709 ,  H04L1/205

Abstract: A system and circuit for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.

Abstract translation: 用于通过异步采样确定数据信号抖动的系统和电路提供了用于测量数据信号抖动的低成本和生产可集成机制。 数据信号被边缘检测并通过不相关频率的采样时钟采样，采样值根据时基上的样本的折叠而被收集在直方图中。 通过扫描确定时基以检测折叠数据的最小抖动。 正确的估计时基周期的直方图代表数据信号边缘位置的概率密度函数，抖动特性由密度函数峰的宽度和形状决定。 可以通过调整用于在整个样本集中折叠数据的时基来纠正频率漂移。

公开(公告)号：US07609758B2

公开(公告)日：2009-10-27

申请号：US10836178

申请日：2004-04-30

Applicant: Roger L. Jungerman

Inventor： Roger L. Jungerman

IPC: H04B3/46

CPC classification number: H04L1/205

Abstract: A method of phase shifting bits in a digital signal pattern combines a bit-wise phase-shift signal with an external clock signal to produce a perturbed clock signal. The perturbed clock signal is provided to a digital pattern source to generate a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal.

Abstract translation: 数字信号模式中的相移位的方法将逐位相移信号与外部时钟信号相组合，以产生扰动的时钟信号。 扰动的时钟信号被提供给数字模式源以产生移位的数字信号模式，其中至少一个位根据逐位相移信号被选择性地相移。

公开(公告)号：US20090175325A1

公开(公告)日：2009-07-09

申请号：US11968872

申请日：2008-01-03

Applicant: Michael A. Sorna ,  William R. Kelly ,  Daniel W. Storaska

Inventor： Michael A. Sorna ,  William R. Kelly ,  Daniel W. Storaska

IPC: H04L1/00

CPC classification number: H04L1/205

Abstract: An eyewidth of a data signal is determined by steps including: (a) recovering a phase of a clock from a data signal as a sampling clock; (b) shifting the phase of the sampling clock away from the first phase by a count multiplied by predetermined phase amount; (c) sampling the data signal with the shifted sampling clock phase to obtain sample data; d) determining whether the sample data contains error; (e) when the sample data does not contain error, recovering the phase of the clock from the data signal again for use as the first phase of the sampling clock, increasing the count value and repeating steps (b) through (e); and f) when the sample data contains error, determining the eyewidth based on the last shifted phase of the sampling clock prior to determining that the sample data contains error.

Abstract translation: 数据信号的眼线宽度由以下步骤决定，包括：（a）从作为采样时钟的数据信号中恢复时钟的相位; （b）使采样时钟的相位离开第一相位移动乘以预定相位量; （c）用移位的采样时钟相位对数据信号进行采样，以获得采样数据; d）确定样本数据是否包含错误; （e）当采样数据不包含错误时，再次从数据信号中恢复时钟的相位以用作采样时钟的第一相位，增加计数值并重复步骤（b）至（e）; 以及f）当样本数据包含错误时，在确定样本数据包含错误之前，基于采样时钟的最后移位的相位来确定眼宽。

公开(公告)号：US20090116591A1

公开(公告)日：2009-05-07

申请号：US11935088

申请日：2007-11-05

Applicant: Marlin Viss ,  David Leyba

Inventor： Marlin Viss ,  David Leyba

IPC: H04L27/06

CPC classification number: H04L1/205 ,  G01R31/31709

Abstract: A sampling method that determines the deterministic and random components of a signal when the magnitude of the signal exceeds the range of the sampler.

Abstract translation: 当信号的幅度超过采样器的范围时，确定信号的确定性和随机分量的采样方法。

公开(公告)号：US07519489B2

公开(公告)日：2009-04-14

申请号：US11519587

申请日：2006-09-12

Applicant: Guenter Tietz ,  Joachim Moll ,  Marcus Mueller

Inventor： Guenter Tietz ,  Joachim Moll ,  Marcus Mueller

IPC: G01R29/26

CPC classification number: H04L1/205

Abstract: Determining a jitter property of a signal with a repetitive bit sequence of a plurality of bits includes setting a sample point at a first sampling position relative to a first transition within the bit pattern, assigning a set of digital values to comparison results of the digital signal with a threshold at the set sample point for a plurality of repetitions of the bit sequence, determining a distribution value on the base of the sum of the assigned digital values, shifting the sample point by a time increment, iteratively repeating determining the distribution value until the sample point has reached a second sampling position, determining from the distribution values a distribution function over the sample points, and determining the jitter property by using the distribution function.

Abstract translation: 确定具有多个比特重复比特序列的信号的抖动特性包括：在相对于比特模式中的第一个转换的第一采样位置设置采样点，将一组数字值分配给数字信号的比较结果 在所设置的采样点处具有多个位序列的重复的阈值，基于所分配的数字值的和来确定分布值，将采样点移位时间增量，迭代地重复确定分布值直到 采样点达到第二采样位置，根据分布值确定采样点上的分布函数，并使用分布函数确定抖动特性。

公开(公告)号：US07512177B2

公开(公告)日：2009-03-31

申请号：US11828390

申请日：2007-07-26

Applicant: Hayden C. Cranford, Jr. ,  Marcel A. Kossel ,  Vernon R. Norman ,  Martin L. Schmatz

Inventor： Hayden C. Cranford, Jr. ,  Marcel A. Kossel ,  Vernon R. Norman ,  Martin L. Schmatz

IPC: H04B3/46

CPC classification number: H04L25/068 ,  H04B3/462 ,  H04L1/205

Abstract: Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.

Abstract translation: 装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为 控制脉冲模式发生器。 在一个方面，可调电容是至少一个变容二极管。 另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到 一对变容二极管。 确定性抖动发生器可以耦合到脉冲图案发生器。 可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。