公开(公告)号：US20250031455A1

公开(公告)日：2025-01-23

申请号：US18908714

申请日：2024-10-07

Applicant: ADVANTEST CORPORATION ,  ISTITUTE OF SCIENCE TOKYO

Inventor： Shinji SUGATANI ,  Takayuki OHBA

IPC: H01L27/06 ,  G11C29/12 ,  H01L21/50 ,  H01L21/66 ,  H01L23/538 ,  H01L25/065

Abstract: When testing a memory chip, the memory chip is determined to be defective if even a portion of the memory chip is defective, and is discarded, which lowers the yield of the three-dimensional memory device. A three-dimensional device is provided comprising a plurality of stacked circuit chips each having one or more circuit blocks in each of a plurality of divided regions obtained by dividing a circuit plane and an interconnect portion communicatively connected, for each group of circuit blocks included in each of the divided regions overlapping in a stacking direction in the plurality of circuit chips, to a predetermined number of circuit blocks sorted from the circuit blocks within the group.