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    METHOD AND STRUCTURE FOR DISSIPATING HEAT AWAY FROM A RESISTOR HAVING NEIGHBORING DEVICES AND INTERCONNECTS
    2.
    发明申请
    METHOD AND STRUCTURE FOR DISSIPATING HEAT AWAY FROM A RESISTOR HAVING NEIGHBORING DEVICES AND INTERCONNECTS 有权
    用于从具有相邻设备和互连的电阻器散热的方法和结构

    公开(公告)号：US20120002375A1

    公开(公告)日：2012-01-05

    申请号：US12827742

    申请日：2010-06-30

    Applicant: Jian-Hong LIN ,  Chin Chuan PENG ,  Tzu-Li LEE ,  Bi-Ling LIN ,  Bor-Jou WEI ,  Chien Shih TSAI

    Inventor： Jian-Hong LIN ,  Chin Chuan PENG ,  Tzu-Li LEE ,  Bi-Ling LIN ,  Bor-Jou WEI ,  Chien Shih TSAI

    IPC: H05K7/20 ,  H01L21/02

    CPC classification number: H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.

    Abstract translation: 一种半导体结构，用于从具有相邻器件和互连的电阻器散热。 半导体结构包括半导体衬底，设置在半导体衬底之上的电阻器和设置在电阻器上方的热保护结构。 热保护结构具有多个散热元件，散热元件的一端设置成与热保护结构导热接触，另一端与半导体衬底导热接触。 热保护结构接收从电阻器产生的热量，并且散热元件将热量散发到半导体衬底。

    Drain leakage reduction by indium transient enchanced diffusion (TED) for low power applications
    3.
    发明授权
    Drain leakage reduction by indium transient enchanced diffusion (TED) for low power applications 有权
    通过铟瞬态增强扩散（TED）对低功率应用进行漏极泄漏降低

    公开(公告)号：US06284579B1

    公开(公告)日：2001-09-04

    申请号：US09418034

    申请日：1999-10-14

    Applicant: Jyh-Haur Wang ,  Bi-Ling Lin ,  Chung-Cheng Wu ,  Carlos H. Diaz

    Inventor： Jyh-Haur Wang ,  Bi-Ling Lin ,  Chung-Cheng Wu ,  Carlos H. Diaz

    IPC: H01L21338

    CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/7833

    Abstract: A method for forming within a substrate employed within a microelectronics fabrication a field effect transistor with attenuated drain leakage current. There is provided a silicon substrate within which are fabricated nMOS field effect transistors (FET) with lightly-doped n-type drain regions (nLDD) employing arsenic (As) dopant. There is then implanted indium (In) dopant atoms adjacent to the As diffused junction to form a p-type pocket therein. There is then avoided the customary high temperature rapid thermal annealing (RTA) step and instead employed a thermal annealing for 2 hours at 750 degrees centigrade, whereupon the implanted indium atom undergo transient enhanced diffusion (TED) to form a graded junction profile, resulting in attenuated drain leakage current and no increased reverse short channel effect from the strong segregation of indium into silicon oxide.

    Abstract translation: 一种在微电子制造中采用的衬底内形成具有衰减漏极漏电流的场效应晶体管的方法。 提供了硅衬底，其中制造了使用砷（As）掺杂剂的具有轻掺杂n型漏极区（nLDD）的nMOS场效应晶体管（FET）。 然后将与In扩散结相邻的铟（In）掺杂剂原子注入到其中以形成p型凹穴。 然后避免了常规的高温快速热退火（RTA）步骤，并且替代地在750℃下进行2小时的热退火，随后注入的铟原子经历瞬时增强扩散（TED）以形成渐变连接轮廓，导致 衰减的漏极漏电流，并没有增加反向短沟道效应，从铟的强烈偏析到氧化硅。

    Method to reduce the gate induced drain leakage current in CMOS devices
    9.
    发明授权
    Method to reduce the gate induced drain leakage current in CMOS devices 有权
    降低CMOS器件漏极漏电流的方法

    公开(公告)号：US06548363B1

    公开(公告)日：2003-04-15

    申请号：US09547237

    申请日：2000-04-11

    Applicant: Chung-Cheng Wu ,  Bi-Ling Lin ,  Carlos Hernando Diaz

    Inventor： Chung-Cheng Wu ,  Bi-Ling Lin ,  Carlos Hernando Diaz

    IPC: H01L21336

    CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L29/7833

    Abstract: A method for forming FET devices with attenuated gate induced drain leakage current. There is provided a silicon semiconductor substrate employed within a microelectronics fabrication. There is formed within the silicon substrate field oxide (FOX) dielectric isolation regions defining an active silicon substrate device area. There is formed over the substrate a silicon oxide gate oxide insulation layer employing thermal oxidation. There is then formed over the silicon oxide gate oxide insulation layer a patterned polycrystalline silicon gate electrode layer. There is then thermally oxidized the substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and in the adjacent silicon substrate area. There is then etched back the thicker silicon oxide layer from the silicon substrate area adjacent to the gate electrode. There is then formed employing low energy ion implantation shallow junction source-drain extension regions adjacent to the gate electrode. There is then formed source-drain regions to complete the FET device, which exhibits attenuated drain leakage current. The present invention may be employed to fabricate complementary metal-oxide-silicon (CMOS) FET devices of either polarity with attenuated gate induced drain leakage (GIDL) current, short channel effect (SCE) and punch-through leakage current in integrated circuit microelectronics fabrications wherein low power drain is desired.

    Abstract translation: 一种用于形成具有衰减栅极感应漏极漏电流的FET器件的方法。 提供了在微电子制造中使用的硅半导体衬底。 形成硅衬底场氧化物（FOX）电介质隔离区域，限定有源硅衬底器件区域。 在衬底上形成采用热氧化的氧化硅栅极氧化物绝缘层。 然后在氧化硅栅极氧化物绝缘层上形成图案化的多晶硅栅极电极层。 然后，将基板和多晶硅栅电极热氧化，以在栅电极的边缘和相邻的硅衬底区域中形成较厚的氧化硅层。 然后从与栅电极相邻的硅衬底区域中回蚀更厚的氧化硅层。 然后形成采用与栅电极相邻的低能离子注入浅结源极 - 漏极扩展区。 然后形成源极 - 漏极区以完成FET器件，其表现出衰减的漏极漏电流。 本发明可用于在集成电路微电子器件制造中制造具有衰减栅极感应漏极泄漏（GIDL）电流，短沟道效应（SCE）和穿通漏电流两种极性的互补金属氧化物 - 硅（CMOS）FET器件 其中期望低功率消耗。

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