公开(公告)号：US20180217182A1

公开(公告)日：2018-08-02

申请号：US15885233

申请日：2018-01-31

Applicant: Shuo ZHENG ,  Babak Baradaran SHOKOUHI ,  Mengmeng DENG ,  Bo CUI

Inventor： Shuo ZHENG ,  Babak Baradaran SHOKOUHI ,  Mengmeng DENG ,  Bo CUI

IPC: G01Q60/38 ,  G01Q70/06

CPC classification number: G01Q60/38 ,  G01Q70/06 ,  G01Q70/10

Abstract: A fabrication method for the fabrication of special nano-scale structures, such as AFM probe tip(s) at the edge of a silicon and/or silicon nitride platform, called the cantilever. An array of these special AFM probes with the AFM tip structure located at the edge is fabricated from an array of regular AFM probes where the AFM tip structure may not originally have been located at the edge of the cantilever. A hard mask is formed on the probe's tip from a hard material, such as a metal mask, where more than one side of the tip could be uncovered. The non-covered side(s) of the probe tip structure(s) are subsequently etched to remove substrate materials, so that a sharp shaft (tip) is formed on the edge of the cantilever, when the process is done in a batch manner it results in an array of such AFM probe tips.

公开(公告)号：US08345253B2

公开(公告)日：2013-01-01

申请号：US12527961

申请日：2008-02-21

Applicant: Lidija Malic ,  Maryam Tabrizian ,  Teodor Veres ,  Bo Cui ,  Francois Normandin

Inventor： Lidija Malic ,  Maryam Tabrizian ,  Teodor Veres ,  Bo Cui ,  Francois Normandin

IPC: G01N21/55

CPC classification number: G01N21/554 ,  B01J2219/00619 ,  B01J2219/00653 ,  B01J2219/00659 ,  B01L3/502792 ,  B01L2300/0636 ,  B01L2300/0819 ,  B01L2300/089 ,  B01L2300/0896 ,  B01L2300/161 ,  B01L2400/0427 ,  B01L2400/086 ,  B82Y30/00 ,  C40B20/08 ,  C40B30/04 ,  C40B40/08 ,  C40B60/02 ,  Y10T436/2575

Abstract: A system and method for molecule detection uses a surface plasmon resonance (SPR) system with detection spots having fixed nanostructures. An SPR assembly may be combined with a digital microfluidic control system such as an electrowetting-on-dielectric (EWOD) chip. The microfluidic system individually directs sample droplets to different detection spots of the SPR assembly, thus allowing the SPR examination of different samples or sample reactions on the same surface. The nanostructures at the detection spots enhance the sensitivity of the SPR signals.

Abstract translation: 用于分子检测的系统和方法使用具有固定纳米结构的检测点的表面等离子体共振（SPR）系统。 SPR组件可以与诸如电润湿介电（EWOD）芯片的数字微流控制系统组合。 微流体系统将样品液滴单独引导到SPR组件的不同检测点，从而允许SPR在同一表面上检查不同的样品或样品反应。 检测点的纳米结构提高了SPR信号的灵敏度。

公开(公告)号：US20100045995A1

公开(公告)日：2010-02-25

申请号：US12527961

申请日：2008-02-21

Applicant: Lidija Malic ,  Maryam Tabrizian ,  Teodor Veres ,  Bo Cui ,  Francois Normandin

Inventor： Lidija Malic ,  Maryam Tabrizian ,  Teodor Veres ,  Bo Cui ,  Francois Normandin

IPC: G01N1/10 ,  G01N21/55

CPC classification number: G01N21/554 ,  B01J2219/00619 ,  B01J2219/00653 ,  B01J2219/00659 ,  B01L3/502792 ,  B01L2300/0636 ,  B01L2300/0819 ,  B01L2300/089 ,  B01L2300/0896 ,  B01L2300/161 ,  B01L2400/0427 ,  B01L2400/086 ,  B82Y30/00 ,  C40B20/08 ,  C40B30/04 ,  C40B40/08 ,  C40B60/02 ,  Y10T436/2575

Abstract: A system and method for molecule detection uses a surface plasmon resonance (SPR) system with detection spots having fixed nanostructures. An SPR assembly may be combined with a digital microfluidic control system such as an electrowetting-on-dielectric (EWOD) chip. The microfluidic system individually directs sample droplets to different detection spots of the SPR assembly, thus allowing the SPR examination of different samples or sample reactions on the same surface. The nanostructures at the detection spots enhance the sensitivity of the SPR signals.

Abstract translation: 用于分子检测的系统和方法使用具有固定纳米结构的检测点的表面等离子体共振（SPR）系统。 SPR组件可以与诸如电润湿介电（EWOD）芯片的数字微流控制系统组合。 微流体系统将样品液滴单独引导到SPR组件的不同检测点，从而允许SPR在同一表面上检查不同的样品或样品反应。 检测点的纳米结构提高了SPR信号的灵敏度。

公开(公告)号：US20070082457A1

公开(公告)日：2007-04-12

申请号：US11533323

申请日：2006-09-19

Applicant: Stephen Chou ,  Bo Cui ,  Christopher Keimel

Inventor： Stephen Chou ,  Bo Cui ,  Christopher Keimel

IPC: H01L21/76

CPC classification number: H01L21/321 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76882

Abstract: A processing method for use in the fabrication of fabrication of nanoscale electronic, optical, magnetic, biological, and fluidic devices and structures, for filling nanoscale holes and trenches, for planarizing a wafer surface, or for achieving both filling and planarizing of a wafer surface simultaneously. The method has the initial step of depositing a layer of a meltable material on a wafer surface. The material is then pressed using a transparent mold while shining a light pulse through the transparent mold to melt the deposited layer of meltable material. A flow of the molten layer material fills the holes and trenches, and conforms to surface features on the transparent mold. The transparent mold is subsequently removed.

Abstract translation: 一种用于制造纳米尺度电子，光学，磁性，生物和流体装置和结构的处理方法，用于填充纳米尺度的孔和沟槽，用于平坦化晶片表面，或用于实现晶片表面的填充和平面化 同时。 该方法具有在晶片表面上沉积可熔材料层的初始步骤。 然后使用透明模具压制材料，同时通过透明模具照射光脉冲以熔化可熔化材料的沉积层。 熔融层材料的流动填充孔和沟槽，并符合透明模具上的表面特征。 随后去除透明模具。

公开(公告)号：US07510946B2

公开(公告)日：2009-03-31

申请号：US11533323

申请日：2006-09-19

Applicant: Stephen Y. Chou ,  Bo Cui ,  Christopher F. Keimel

Inventor： Stephen Y. Chou ,  Bo Cui ,  Christopher F. Keimel

IPC: H01L21/3105

CPC classification number: H01L21/321 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76882

Abstract: A processing method for use in the fabrication of fabrication of nanoscale electronic, optical, magnetic, biological, and fluidic devices and structures, for filling nanoscale holes and trenches, for planarizing a wafer surface, or for achieving both filling and planarizing of a wafer surface simultaneously. The method has the initial step of depositing a layer of a meltable material on a wafer surface. The material is then pressed using a transparent mold while shining a light pulse through the transparent mold to melt the deposited layer of meltable material. A flow of the molten layer material fills the holes and trenches, and conforms to surface features on the transparent mold. The transparent mold is subsequently removed.

Abstract translation: 一种用于制造纳米尺度电子，光学，磁性，生物和流体装置和结构的处理方法，用于填充纳米尺度的孔和沟槽，用于平坦化晶片表面，或用于实现晶片表面的填充和平面化 同时。 该方法具有在晶片表面上沉积可熔材料层的初始步骤。 然后使用透明模具压制材料，同时通过透明模具照射光脉冲以熔化可熔化材料的沉积层。 熔融层材料的流动填充孔和沟槽，并符合透明模具上的表面特征。 随后去除透明模具。

公开(公告)号：US10782313B2

公开(公告)日：2020-09-22

申请号：US15885233

申请日：2018-01-31

Applicant: Shuo Zheng ,  Babak Baradaran Shokouhi ,  Mengmeng Deng ,  Bo Cui

Inventor： Shuo Zheng ,  Babak Baradaran Shokouhi ,  Mengmeng Deng ,  Bo Cui

IPC: G01Q60/38 ,  G01Q70/10 ,  G01Q70/06

Abstract: A fabrication method for the fabrication of special nano-scale structures, such as AFM probe tip(s) at the edge of a silicon and/or silicon nitride platform, called the cantilever. An array of these special AFM probes with the AFM tip structure located at the edge is fabricated from an array of regular AFM probes where the AFM tip structure may not originally have been located at the edge of the cantilever. A hard mask is formed on the probe's tip from a hard material, such as a metal mask, where more than one side of the tip could be uncovered. The non-covered side(s) of the probe tip structure(s) are subsequently etched to remove substrate materials, so that a sharp shaft (tip) is formed on the edge of the cantilever, when the process is done in a batch manner it results in an array of such AFM probe tips.

公开(公告)号：US09522821B2

公开(公告)日：2016-12-20

申请号：US14785338

申请日：2014-04-09

Applicant: Bo Cui ,  Ripon Kumar Dey

Inventor： Bo Cui ,  Ripon Kumar Dey

IPC: H01L21/00 ,  B81C1/00 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3213 ,  B81B1/00 ,  B82Y40/00 ,  G01Q70/12 ,  B82Y30/00

CPC classification number: B81C1/00111 ,  B81B1/008 ,  B81B2201/12 ,  B81B2203/0361 ,  B81C2201/0132 ,  B81C2201/053 ,  B82Y30/00 ,  B82Y40/00 ,  G01Q70/12 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/32139

Abstract: The invention provides a fabrication method of batch producing nano-scale structures, such as arrays of silicon pillars of high aspect ratio. The invention also relates to providing arrays of high aspect ratio silicon pillars fabricated using the improved fabrication method. The array of silicon pillars is fabricated from arrays of low aspect ratio pyramid-shaped structures. Mask formed from a hard material, such as a metal mask, is formed on top of each of the pyramid-shaped structures in a batch process. The pyramid-shaped structures are subsequently etched to remove substrate materials not protected by the hard masks, so that a high aspect ratio pillar or shaft is formed on the pyramid-shaped low aspect ratio base, resulting in an array of high aspect ratio silicon pillars.

Abstract translation: 本发明提供了批量生产纳米级结构的制造方法，例如高纵横比的硅柱阵列。 本发明还涉及使用改进的制造方法制造的高纵横比硅柱阵列。 硅柱阵列由低纵横比金字塔形结构的阵列制成。 由金属掩模等硬质材料形成的掩模在分批处理中形成在每个金字塔形结构的顶部上。 金字塔形结构随后被蚀刻以除去未被硬掩模保护的衬底材料，从而在金字塔形的低纵横比基底上形成高纵横比的柱或轴，从而形成高纵横比硅柱的阵列 。

公开(公告)号：US20160068384A1

公开(公告)日：2016-03-10

申请号：US14785338

申请日：2014-04-09

Applicant: Bo CUI ,  Ripon Kumar DEY

Inventor： Bo CUI ,  Ripon Kumar DEY

IPC: B81C1/00 ,  B81B1/00

CPC classification number: B81C1/00111 ,  B81B1/008 ,  B81B2201/12 ,  B81B2203/0361 ,  B81C2201/0132 ,  B81C2201/053 ,  B82Y30/00 ,  B82Y40/00 ,  G01Q70/12 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/32139

Abstract: The invention provides a fabrication method of batch producing nano-scale structures, such as arrays of silicon pillars of high aspect ratio. The invention also relates to providing arrays of high aspect ratio silicon pillars fabricated using the improved fabrication method. The array of silicon pillars is fabricated from arrays of low aspect ratio pyramid-shaped structures. Mask formed from a hard material, such as a metal mask, is formed on top of each of the pyramid-shaped structures in a batch process. The pyramid-shaped structures are subsequently etched to remove substrate materials not protected by the hard masks, so that a high aspect ratio pillar or shaft is formed on the pyramid-shaped low aspect ratio base, resulting in an array of high aspect ratio silicon pillars.

Abstract translation: 本发明提供了批量生产纳米级结构的制造方法，例如高纵横比的硅柱阵列。 本发明还涉及使用改进的制造方法制造的高纵横比硅柱阵列。 硅柱阵列由低纵横比金字塔形结构的阵列制成。 由金属掩模等硬质材料形成的掩模在分批处理中形成在每个金字塔形结构的顶部上。 金字塔形结构随后被蚀刻以除去未被硬掩模保护的衬底材料，从而在金字塔形的低纵横比基底上形成高纵横比的柱或轴，导致高纵横比硅柱的阵列 。