公开(公告)号：US20110285006A1

公开(公告)日：2011-11-24

申请号：US12783104

申请日：2010-05-19

Applicant: Chao-Fu Weng ,  Yi-Ting Wu

Inventor： Chao-Fu Weng ,  Yi-Ting Wu

IPC: H01L23/538 ,  H01L21/78 ,  H01L21/50

CPC classification number: H01L23/48 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L2224/24227 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165

Abstract: The present invention relates to a semiconductor package and method for making the same. The semiconductor package includes a silicon substrate unit, a bridge chip and at least one active chip. The silicon substrate unit has a cavity and a plurality of vias. The bridge chip is attached to the cavity and has a plurality of non-contact pads. The active chip is disposed above the bridge chip and has a plurality of non-contact pads and a plurality of conducting elements. The conducting elements of the active chip contact the vias of the silicon substrate unit, the non-contact pads of the active chip face but are not in physical contact with the non-contact pads of the bridge chip, so as to provide proximity communication between the active chip and the bridge chip.

Abstract translation: 半导体封装及其制造方法技术领域本发明涉及半导体封装及其制造方法。 半导体封装包括硅衬底单元，桥芯片和至少一个有源芯片。 硅衬底单元具有空腔和多个通孔。 桥芯片附接到腔体并具有多个非接触垫片。 有源芯片设置在桥芯片上方并且具有多个非接触焊盘和多个导电元件。 有源芯片的导电元件接触硅衬底单元的通孔，有源芯片面的非接触焊盘，但不与桥芯片的非接触焊盘物理接触，以便提供 有源芯片和桥芯片。

公开(公告)号：US20100200974A1

公开(公告)日：2010-08-12

申请号：US12505071

申请日：2009-07-17

Applicant: Chao-Fu Weng ,  Tsung-Yueh Tsai ,  Chang-Ying Hung ,  Jen-Chieh Kao

Inventor： Chao-Fu Weng ,  Tsung-Yueh Tsai ,  Chang-Ying Hung ,  Jen-Chieh Kao

IPC: H01L23/52 ,  H01L23/49 ,  H01L23/28

CPC classification number: H01L24/05 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/0516 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48864 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2924/00012

Abstract: A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element.

Abstract translation: 提供了使用其的半导体封装结构。 半导体封装结构包括第一半导体元件，第二半导体元件，绑定线和模制化合物。 第一半导体元件包括半导体管芯和焊盘。 焊盘设置在半导体管芯的上方，并且包括金属基底，设置在金属基底上方的硬金属层和设置在硬金属层上方的抗氧化金属层。 硬质金属层的硬度大于金属基体的硬度。 抗氧化金属层的活性低于硬质金属层的活性。 第一半导体元件设置在第二半导体元件上方。 接合线连接到焊盘和第二半导体元件。 成型复合体密封第一半导体元件和接合线并覆盖第二半导体元件。

公开(公告)号：US20060017171A1

公开(公告)日：2006-01-26

申请号：US11185848

申请日：2005-07-21

Applicant: Chao-Fu Weng

Inventor： Chao-Fu Weng

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/00014

Abstract: A formation method and structure of conductive bump are provided. A conductive bump is formed on a wafer through an under bump metallurgy layer. A nickel-based wetting layer in the under bump metallurgy layer is applied on the conductive bump to prevent stannum in the conductive bump from diffusing downwards.

Abstract translation: 提供导电凸块的形成方法和结构。 通过下凸块冶金层在晶片上形成导电凸块。 在凸块状金属层上的镍基润湿层被施加在导电凸块上以防止导电凸块中的锡向下扩散。

公开(公告)号：US06877653B2

公开(公告)日：2005-04-12

申请号：US10248411

申请日：2003-01-17

Applicant: Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

Inventor： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC: B23K35/02 ,  B23K35/26 ,  H05K3/34 ,  B23K31/02 ,  B23K31/00 ,  B23K35/24

CPC classification number: H05K3/3484 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/262 ,  B23K35/268 ,  H05K3/3463 ,  H05K2201/0379 ,  H05K2203/043 ,  H05K2203/0568

Abstract: A method of modifying the tin to lead ratio of a tin-lead bump forms a patterned solder mask over a substrate that comprises a first tin-lead bump formed thereon, the patterned solder mask having an opening that exposes the tin-lead bump. A solder material including tin and lead is filled in the opening of the solder mask over the first tin-lead bump. The solder material has a tin to lead ratio that differs from that of the first tin-lead bump. The solder material is reflowed to fuse with the first tin-lead bump, which forms a second tin-lead bump. The tin to lead ratio of the second tin-lead bump is thereby different from that of the first tin-lead bump.

Abstract translation: 改变锡铅凸块的锡引导比的方法在衬底上形成图案化的焊料掩模，该衬底包括形成在其上的第一锡铅凸块，所述图案化焊料掩模具有暴露锡铅凸块的开口。 包括锡和铅的焊料材料填充在第一锡铅凸块上的焊料掩模的开口中。 焊锡材料具有与第一锡铅凸块不同的锡与引线比。 焊料材料被回流以与形成第二锡铅凸块的第一锡铅凸块熔合。 因此，第二锡铅凸块的锡与引线比不同于第一锡铅凸块的锡引导比。

公开(公告)号：US06875683B2

公开(公告)日：2005-04-05

申请号：US10063576

申请日：2002-05-03

Applicant: Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee

Inventor： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee

IPC: H01L21/60 ,  H01L23/485 ,  H01L21/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/48463 ,  H01L2224/78301 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01083 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A method of forming a bump on an active surface of a wafer is disclosed. The method of the invention forms an under ball metallurgy (UBM) onto the active surface of the wafer. Then, the UBM is partially removed until a portion of the active surface of the wafer is exposed. At least one conductive stud is bonded onto the non-removed UBM by wire bonding.

Abstract translation: 公开了一种在晶片的有源表面上形成凸块的方法。 本发明的方法在晶片的有效表面上形成球下冶金（UBM）。 然后，UBM被部分地去除，直到晶片的有效表面的一部分露出。 通过引线接合将至少一个导电柱结合到未去除的UBM上。

公开(公告)号：US06827252B2

公开(公告)日：2004-12-07

申请号：US10063573

申请日：2002-05-03

Applicant: Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee

Inventor： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee

IPC: B23K3100

CPC classification number: B23K1/0016 ,  B23K2101/40 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of forming bumps on the active surface of a silicon wafer. An under-ball metallic layer is formed over the active surface of the wafer. A plurality of first solder blocks is attached to the upper surface of the under-ball metallic layer. Each first solder block has an upper surface and a lower surface. The lower surface of each first solder block bonds with the under-ball metallic layer. The upper surfaces of the first solder blocks are planarized. A second solder block is attached to the upper surface of each first solder block and then a reflow operation is carried out.

Abstract translation: 一种在硅晶片的有源表面上形成凸块的方法。 在晶片的有效表面上形成球底金属层。 多个第一焊料块附接到球底金属层的上表面。 每个第一焊料块具有上表面和下表面。 每个第一焊料块的下表面与下球金属层结合。 第一焊料块的上表面被平坦化。 第二焊料块附着到每个第一焊料块的上表面，然后进行回流操作。

公开(公告)号：US06756256B2

公开(公告)日：2004-06-29

申请号：US10248803

申请日：2003-02-20

Applicant: Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

Inventor： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC: H01L2182

CPC classification number: H01L24/12 ,  H01L23/3171 ,  H01L23/5258 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer covering the bump pads and the fuse pads of the wafer, wherein a central region of the fuse pads is burnt to form a gap which allows the material of the dielectric layer to fill up the gap. Afterwards, either a part of the dielectric layer is removed and the part of the dielectric layer covering the fuse pads remainsor a part of the dielectric layer covering the bump pads is removed. Then, an under ball metallurgy layer is formed on the bump pads of the wafer so that the material of the under ball metallurgy layer does not cover the two sides of the fuse pad at the same time, or fill into the gap. As a result, the electrical isolation still remains.

Abstract translation: 一种在晶片上形成凸起之前防止燃烧保险丝垫进一步电连接的方法。 在覆盖凸块焊盘和晶片的熔断体的晶片的有源表面上形成电介质层，其中熔断器的中心区域被烧结以形成间隙，该间隙允许电介质层的材料填满 间隙。 之后，除去介电层的一部分，并且覆盖覆盖焊盘的电介质层的一部分覆盖熔丝焊盘的介电层的一部分被去除。 然后，在晶片的凸块焊盘上形成球下冶金层，使得球下冶金层的材料不会同时覆盖熔丝焊盘的两侧或者填充到间隙中。 结果，电隔离仍然存在。

公开(公告)号：US20070252275A1

公开(公告)日：2007-11-01

申请号：US11772247

申请日：2007-07-02

Applicant: Min-Lung Huang ,  Chi-Long Tsai ,  Chao-Fu Weng ,  Ching-Huei Su

Inventor： Min-Lung Huang ,  Chi-Long Tsai ,  Chao-Fu Weng ,  Ching-Huei Su

IPC: H01L23/48

CPC classification number: H01L24/12 ,  H01L21/76838 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05172 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract translation: 提供了包括芯片，再分配层，第二钝化层和至少凸块的芯片结构。 芯片具有第一钝化层和至少一个焊盘。 第一钝化层露出接合焊盘并具有至少一个凹部。 再分配层形成在第一钝化层上并电连接到接合焊盘。 此外，再分布层也从接合垫延伸到凹部。 第二钝化层形成在第一钝化层和再分布层之上。 第二钝化层还具有使凹部上方的再分布层露出的开口。 凸块穿过开口并与凹部上方的再分布层电连接。

公开(公告)号：US07253519B2

公开(公告)日：2007-08-07

申请号：US10709953

申请日：2004-06-09

Applicant: Min-Lung Huang ,  Chi-Long Tsai ,  Chao-Fu Weng ,  Ching-Huei Su

Inventor： Min-Lung Huang ,  Chi-Long Tsai ,  Chao-Fu Weng ,  Ching-Huei Su

IPC: H01L23/48 ,  H01L23/28 ,  H01L23/31 ,  H01L23/485

CPC classification number: H01L24/12 ,  H01L21/76838 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05172 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract translation: 提供了包括芯片，再分配层，第二钝化层和至少凸块的芯片结构。 芯片具有第一钝化层和至少一个焊盘。 第一钝化层露出接合焊盘并具有至少一个凹部。 再分配层形成在第一钝化层上并电连接到接合焊盘。 此外，再分配层也从接合垫延伸到凹部。 第二钝化层形成在第一钝化层和再分布层之上。 第二钝化层还具有使凹部上方的再分布层露出的开口。 凸块穿过开口并与凹部上方的再分布层电连接。

公开(公告)号：US07064428B2

公开(公告)日：2006-06-20

申请号：US10248114

申请日：2002-12-19

Applicant: Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

Inventor： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC: H01L23/10 ,  H05K7/20

CPC classification number: H01L24/10 ,  H01L23/3107 ,  H01L24/13 ,  H01L2224/05026 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.

Abstract translation: 描述了适用于包括多个接触点的载体上的倒装芯片布置的晶片级封装结构。 该晶片级封装结构主要由芯片和导电层形成。 导电层设置在芯片的焊盘上作为接触点。 导电层还可以布置在作为散热片的芯片上的接合焊盘外部的区域，以增强封装的散热能力。