公开(公告)号：US20130009250A1

公开(公告)日：2013-01-10

申请号：US13482374

申请日：2012-05-29

Applicant: Tung-Hsing LEE ,  Tse-Hsiang HSU ,  Ching-Chung KO

Inventor： Tung-Hsing LEE ,  Tse-Hsiang HSU ,  Ching-Chung KO

IPC: H01L27/092

CPC classification number: H01L21/823842 ,  H01L27/0207 ,  H01L27/092

Abstract: A semiconductor integrated circuit device including: a diffusion area defined by an isolation region in a substrate; a PMOS transistor comprising a metal gate and a high-k dielectric over the diffusion area and source/drain regions sandwiching the metal gate in a first direction; a plurality of dummy diffusion areas surrounding and spaced apart from the diffusion area; and a plurality of first dummy patterns at the two sides of the PMOS transistor in a second direction perpendicular to the first direction and between the dummy diffusion areas and the diffusion area.

Abstract translation: 一种半导体集成电路器件，包括：由衬底中的隔离区域限定的扩散区域; PMOS晶体管，包括在扩散区域上的金属栅极和高k电介质，以及在第一方向上夹着金属栅极的源极/漏极区域; 围绕并与扩散区间隔开的多个虚拟扩散区域; 以及在垂直于第一方向的第二方向和虚拟扩散区域与扩散区域之间的PMOS晶体管两侧的多个第一虚拟图案。

公开(公告)号：US20100213507A1

公开(公告)日：2010-08-26

申请号：US12500607

申请日：2009-07-10

Applicant: Ching-Chung Ko ,  Tung-Hsing Lee ,  Zheng Zeng

Inventor： Ching-Chung Ko ,  Tung-Hsing Lee ,  Zheng Zeng

IPC: H01L29/739

CPC classification number: H01L29/735 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/6625

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

公开(公告)号：US20090236637A1

公开(公告)日：2009-09-24

申请号：US12052735

申请日：2008-03-21

Applicant: Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

Inventor： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

IPC: H01L27/10

CPC classification number: H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of copper metal layers embedded in respective the plurality of IMD layers; a first passivation layer overlying the plurality of IMD layers and the plurality of copper metal layers; a first power/ground ring of a circuit block of the integrated circuit chip formed in a topmost layer of the plurality of copper metal layers; a second power/ground ring of the circuit block of the integrated circuit chip formed in an aluminum layer over the first passivation layer; and a second passivation layer covering the second power/ground ring and the first passivation layer.

Abstract translation: 公开了具有降低的IR降低和芯片性能改善的集成电路芯片。 集成电路芯片包括其上具有多个金属间电介质（IMD）层和嵌入在多个IMD层中的多个铜金属层的半导体衬底; 覆盖所述多个IMD层和所述多个铜金属层的第一钝化层; 所述集成电路芯片的电路块的第一电源/接地环形成在所述多个铜金属层的最上层中; 所述集成电路芯片的电路块的第二电源/接地环形成在所述第一钝化层上的铝层中; 以及覆盖所述第二电源/接地环和所述第一钝化层的第二钝化层。

公开(公告)号：US08860544B2

公开(公告)日：2014-10-14

申请号：US12493245

申请日：2009-06-29

Applicant: Ching-Chung Ko ,  Tung-Hsing Lee ,  Kuei-Ti Chan ,  Tao Cheng ,  Ming-Tzong Yang

Inventor： Ching-Chung Ko ,  Tung-Hsing Lee ,  Kuei-Ti Chan ,  Tao Cheng ,  Ming-Tzong Yang

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.

Abstract translation: 集成电感器包括由钝化层顶部的铝层组成的绕组，其中铝层不延伸到钝化层中，并且具有不小于约2.0微米的厚度。 钝化层的厚度不小于约0.8微米。 通过从集成电感器中消除铜并增加钝化层的厚度，电感器结构的底表面与半导体衬底的主表面之间的距离增加，因此寄生衬底耦合可能会降低，Q因子 可以改进。 此外，铝层的增加的厚度也可以有助于改善Q因子。

公开(公告)号：US07932581B2

公开(公告)日：2011-04-26

申请号：US12464107

申请日：2009-05-12

Applicant: Ming-Tzong Yang ,  Ching-Chung Ko ,  Tung-Hsing Lee ,  Zheng Zeng

Inventor： Ming-Tzong Yang ,  Ching-Chung Ko ,  Tung-Hsing Lee ,  Zheng Zeng

IPC: H01L29/66

CPC classification number: H01L29/735 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0692 ,  H01L29/6625

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region surrounding the base region with an offset between an edge of the gate and the collector region; a lightly doped drain region between the edge of the gate and the collector region; a salicide block layer disposed on or over the lightly doped drain region; and a collector salicide formed on at least a portion of the collector region.

Abstract translation: 横向双极结晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 集电极区域，围绕所述基极区域，在所述栅极的边缘和所述集电极区域之间具有偏移; 在栅极的边缘和集电极区域之间的轻掺杂漏极区; 设置在所述轻掺杂漏极区域上或上部的自对准硅化物阻挡层; 以及形成在所述收集器区域的至少一部分上的收集器自对准硅化物。

公开(公告)号：US07897995B2

公开(公告)日：2011-03-01

申请号：US12420046

申请日：2009-04-07

Applicant: Ming-Tzong Yang ,  Tao Cheng ,  Ching-Chung Ko ,  Tung-Hsing Lee

Inventor： Ming-Tzong Yang ,  Tao Cheng ,  Ching-Chung Ko ,  Tung-Hsing Lee

IPC: H01L29/735

CPC classification number: H01L29/735 ,  H01L29/0692 ,  H01L29/423

Abstract: A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region.

Abstract translation: 形成在半导体衬底中的横向双极结型晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 具有至少一个开放侧并且围绕所述基底区域的周边设置的收集器区域; 设置在集电极区域周围的浅沟槽隔离（STI）区域; 设置在所述STI区域周围的基极接触区域; 以及与所述基极接触区域合并并横向延伸到所述集电极区域的开放侧的栅极的延伸区域。

公开(公告)号：US20120043663A1

公开(公告)日：2012-02-23

申请号：US13286231

申请日：2011-11-01

Applicant: Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Ta-Hsi Chou ,  Peng-Cheng Kao ,  Ling-Wei Ke

Inventor： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Ta-Hsi Chou ,  Peng-Cheng Kao ,  Ling-Wei Ke

IPC: H01L23/52

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/05124 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.

Abstract translation: 集成电路芯片包括其上具有多个IMD层和多个第一导电层的半导体衬底; 覆盖所述多个IMD层和所述第一导电层的第一钝化层; 在覆盖所述第一绝缘层的第一铝层中的至少第一电源/接地网布线; 以及覆盖在第一铝层上的第二铝层中的至少第二电源/接地网布线。

公开(公告)号：US08072004B2

公开(公告)日：2011-12-06

申请号：US12883163

申请日：2010-09-15

Applicant: Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

Inventor： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

IPC: H01L27/10

CPC classification number: H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers comprise copper; a first passivation layer overlying the plurality of IMD layers and the plurality of first conductive layers; a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying the first passivation layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second passivation layer covering the second conductive layer and the first passivation layer.

Abstract translation: 集成电路芯片包括其上具有多个金属间电介质（IMD）层的半导体衬底和嵌入在多个IMD层中的多个第一导电层，其中第一导电层包括铜; 覆盖所述多个IMD层和所述多个第一导电层的第一钝化层; 形成在覆盖所述第一钝化层的第二导电层中的多个第一电源/接地网布线，用于分配功率信号或接地信号，其中所述第二导电层包括铝; 以及覆盖所述第二导电层和所述第一钝化层的第二钝化层。

公开(公告)号：US20100213504A1

公开(公告)日：2010-08-26

申请号：US12389378

申请日：2009-02-20

Applicant: Ching-Chung Ko ,  Tung-Hsing Lee

Inventor： Ching-Chung Ko ,  Tung-Hsing Lee

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract translation: 横向双极结晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 以及围绕所述基底区域的收集器区域; 其中所述栅极下方的所述基极区域的所述部分未经过阈值电压注入工艺。

公开(公告)号：US20090261937A1

公开(公告)日：2009-10-22

申请号：US12493245

申请日：2009-06-29

Applicant: Ching-Chung Ko ,  Tung-Hsing Lee ,  Kuei-Ti Chan ,  Tao Cheng ,  Ming-Tzong Yang

Inventor： Ching-Chung Ko ,  Tung-Hsing Lee ,  Kuei-Ti Chan ,  Tao Cheng ,  Ming-Tzong Yang

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.

Abstract translation: 集成电感器包括由钝化层顶部的铝层组成的绕组，其中铝层不延伸到钝化层中，并且具有不小于约2.0微米的厚度。 钝化层的厚度不小于约0.8微米。 通过从集成电感器中消除铜并增加钝化层的厚度，电感器结构的底表面与半导体衬底的主表面之间的距离增加，因此寄生衬底耦合可能会降低，Q因子 可以改进。 此外，铝层的增加的厚度也可以有助于改善Q因子。