公开(公告)号：US20130034948A1

公开(公告)日：2013-02-07

申请号：US13204352

申请日：2011-08-05

Applicant: Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

Inventor： Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.

Abstract translation: 公开了一种制造半导体器件的方法。 一种示例性方法包括提供衬底。 在半导体衬底上形成电介质层，并在电介质层上形成阻挡层。 阻挡层和电介质层包括不同的材料。 该方法还包括在停止层上形成图案化的硬掩模层，并通过图案化的硬掩模层蚀刻半导体衬底以形成多个沟槽。 该方法还包括在半导体衬底上沉积隔离材料并基本上填充多个沟槽。 此后，在半导体衬底上执行CMP处理，其中CMP处理在停止层上停止。

公开(公告)号：US08853052B2

公开(公告)日：2014-10-07

申请号：US13204352

申请日：2011-08-05

Applicant: Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

Inventor： Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/76 ,  H01L29/00 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.

Abstract translation: 公开了一种制造半导体器件的方法。 一种示例性方法包括提供衬底。 在半导体衬底上形成电介质层，并在电介质层上形成阻挡层。 阻挡层和电介质层包括不同的材料。 该方法还包括在停止层上形成图案化的硬掩模层，并通过图案化的硬掩模层蚀刻半导体衬底以形成多个沟槽。 该方法还包括在半导体衬底上沉积隔离材料并基本上填充多个沟槽。 此后，在半导体衬底上执行CMP处理，其中CMP处理在停止层上停止。

公开(公告)号：US08481391B2

公开(公告)日：2013-07-09

申请号：US13110294

申请日：2011-05-18

Applicant: Chin-I Liao ,  Ching-Hong Jiang ,  Ching-I Li ,  Shu-Yen Chan ,  Chin-Cheng Chien

Inventor： Chin-I Liao ,  Ching-Hong Jiang ,  Ching-I Li ,  Shu-Yen Chan ,  Chin-Cheng Chien

IPC: H01L21/336

CPC classification number: H01L29/7842 ,  H01L21/3247 ,  H01L29/66636 ,  H01L29/7848

Abstract: A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface.

Abstract translation: 制造应力提供结构的方法被应用于半导体器件的制造。 首先，提供具有沟道结构的衬底。 通过化学气相沉积在含卤素的环境中在衬底上形成氮化硅层。 执行蚀刻处理以部分地去除氮化硅层以暴露基板的表面的一部分在通道结构旁边。 蚀刻衬底的暴露表面以在衬底中形成凹陷。 然后，将衬底在750℃和820℃之间的温度下进行热处理。在对衬底进行热处理之后，在凹部中填充应力提供材料，以在凹部内形成应力提供结构。 半导体器件包括衬底，凹部和应力提供结构。 凹槽具有圆形的内表面。 应力提供结构具有圆形外表面。

公开(公告)号：US20130043512A1

公开(公告)日：2013-02-21

申请号：US13212834

申请日：2011-08-18

Applicant: Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

Inventor： Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/31 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/02274 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/324 ,  H01L29/66795

Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

公开(公告)号：US20120292638A1

公开(公告)日：2012-11-22

申请号：US13110294

申请日：2011-05-18

Applicant: Chin-I LIAO ,  Ching-Hong Jiang ,  Ching-I Li ,  Shu-Yen Chan ,  Chin-Cheng Chien

Inventor： Chin-I LIAO ,  Ching-Hong Jiang ,  Ching-I Li ,  Shu-Yen Chan ,  Chin-Cheng Chien

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7842 ,  H01L21/3247 ,  H01L29/66636 ,  H01L29/7848

Abstract: A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface.

Abstract translation: 制造应力提供结构的方法被应用于半导体器件的制造。 首先，提供具有沟道结构的衬底。 通过化学气相沉积在含卤素的环境中在衬底上形成氮化硅层。 执行蚀刻处理以部分地去除氮化硅层以暴露基板的表面的一部分在通道结构旁边。 蚀刻衬底的暴露表面以在衬底中形成凹陷。 然后，将衬底在750℃和820℃之间的温度下进行热处理。在对衬底进行热处理之后，在凹部中填充应力提供材料，以在凹部内形成应力提供结构。 半导体器件包括衬底，凹部和应力提供结构。 凹槽具有圆形的内表面。 应力提供结构具有圆形外表面。

公开(公告)号：US09006802B2

公开(公告)日：2015-04-14

申请号：US13212834

申请日：2011-08-18

Applicant: Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

Inventor： Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02274 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/324 ,  H01L29/66795

Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

Abstract translation: 公开了形成绝缘材料层的半导体器件制造方法和方法。 在一个实施例中，形成半导体器件的复合绝缘材料层的方法包括提供工件并使用第一等离子体功率电平在工件上形成绝缘材料层的第一子层。 使用第二等离子体功率电平在绝缘材料层的第一子层上形成绝缘材料层的第二子层，并且将工件退火。