公开(公告)号：US20050105628A1

公开(公告)日：2005-05-19

申请号：US10498143

申请日：2002-12-09

Applicant: Stephan Koch ,  Gerd Scheller ,  Rolf Becker

Inventor： Stephan Koch ,  Gerd Scheller ,  Rolf Becker

IPC: H04L7/04 ,  G06F13/40 ,  H04L27/00

CPC classification number: G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system with a transmitter for transmitting digital data via an interface to a receiver. The interface has at least one data line and a clock line. A clock generator supplies a clock signal to the clock line. The receiver uses the clock signal received from the clock line for deriving timing information for processing received digital data. The clock signal may have an amplitude that is lower than the power supply voltage VDD, typically less than half of the power supply voltage, and less stringent requirements can be applied to the waveform of the clock signal than traditionally applied to data and clock signals. The clock signals are hereby less power consuming and cause significantly less electromagnetic interference.

Abstract translation: 具有用于经由接口将数字数据发送到接收器的发射器的系统。 该接口至少有一条数据线和一条时钟线。 时钟发生器向时钟线提供时钟信号。 接收机使用从时钟线接收的时钟信号来导出用于处理接收的数字数据的定时信息。 时钟信号可能具有低于电源电压VDD的幅度，通常小于电源电压的一半，并且对于比传统上应用于数据和时钟信号的时钟信号的波形不太严格的要求。 因此，时钟信号的功耗较小，并且导致显着较小的电磁干扰。

公开(公告)号：US06383864B1

公开(公告)日：2002-05-07

申请号：US08940897

申请日：1997-09-30

Applicant: Gerd Scheller ,  Martin Gall ,  Reinhard J. Stengl

Inventor： Gerd Scheller ,  Martin Gall ,  Reinhard J. Stengl

IPC: H01L218242

Abstract: A memory cell, which includes a transistor and a capacitor, for use in a DRAM uses a silicon-filled vertical trench as the capacitor and a vertical transistor superposed over the vertical trench in a silicon chip. An epitaxial layer is formed at the top of the fill in the trench to impart seed information to the primarily polysilicon silicon fill in the trench. A polysilicon layer is deposited over the top surface of the chip, is apertured over the top of the trench, and has its sidewalls oxidized. The opening is then refilled with epitaxial silicon in which there is created in operation an inversion layer that serves as the channel of the transistor, and the deposited polysilicon layer serves as the word line. Another silicon layer is deposited over the epitaxial layer to serve as the bit line. The source/drain regions of the transistor are formed at the merger of the deposited layer with the fill in the trench and the merger with the polysilicon layer that serves as the bit line.