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    METHODS OF FORMING SEMICONDUCTOR DEVICE USING BOWING CONTROL LAYER
    1.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICE USING BOWING CONTROL LAYER 有权
    使用控制层形成半导体器件的方法

    公开(公告)号：US20150056805A1

    公开(公告)日：2015-02-26

    申请号：US14247635

    申请日：2014-04-08

    Applicant: Jae-Hong Park ,  Min-Joon Park ,  Jun-Ho Yoon ,  Gyung-Jin Min ,  Jin-Young Park ,  Je-Woo Han

    Inventor： Jae-Hong Park ,  Min-Joon Park ,  Jun-Ho Yoon ,  Gyung-Jin Min ,  Jin-Young Park ,  Je-Woo Han

    IPC: H01L21/768

    CPC classification number: H01L21/76802 ,  H01L21/31144 ,  H01L21/76804 ,  H01L27/10852 ,  H01L28/90

    Abstract: A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°.

    Abstract translation: 在中间层上形成弯曲控制图案。 在弓形控制层上形成硬掩模图案。 硬掩模图案具有第一开口，并且弯曲控制图案具有第二开口。 第三开口穿过中间层并连接到第二开口。 弯曲控制图案包括在第二开口的下端上的第一边缘和第二边缘，以及在第二开口的上端上的第三边缘。 当第一边缘上的第一点，第二边缘上的第二点和通过第三边缘的水平线上的第三点被限定时，从第一点到第二点的第一侧之间的相交角，以及 从第二点到第三点的第二侧为约50°至约80°。

    METHOD OF FORMING FINE PATTERN AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF FORMING FINE PATTERN AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    形成精细图案的方法和制造半导体器件的方法

    公开(公告)号：US20120329224A1

    公开(公告)日：2012-12-27

    申请号：US13495510

    申请日：2012-06-13

    Applicant: Yoo-chul Kong ,  Jin-kwan Lee ,  Gyung-jin Min ,  Seong-soo Lee

    Inventor： Yoo-chul Kong ,  Jin-kwan Lee ,  Gyung-jin Min ,  Seong-soo Lee

    IPC: H01L21/308 ,  H01L21/336

    CPC classification number: H01L21/31144 ,  H01L21/0332 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A method of forming a fine pattern and a method of manufacturing a semiconductor device. The method of forming a fine pattern includes: forming a hard mask layer on a to-be-etched layer; forming on the hard mask layer a first mask pattern including a plurality of elongated openings that are arranged at predetermined intervals in a first direction and a second direction different from the first direction and are offset from each other in adjacent columns in the second direction; forming on the hard mask layer a second mask pattern including at least two linear openings that each pass through the elongated openings in the adjacent columns and extend in the first direction; forming a hard mask pattern by etching the hard mask layer by using the second mask pattern as an etch mask; and etching the to-be-etched layer by using the hard mask pattern.

    Abstract translation: 形成精细图案的方法和制造半导体器件的方法。 形成精细图案的方法包括：在被蚀刻层上形成硬掩模层; 在所述硬掩模层上形成第一掩模图案，所述第一掩模图案包括多个细长开口，所述第一掩模图案沿着第一方向以不同于第一方向的第二方向以预定间隔布置，并且在相邻列中沿第二方向彼此偏移; 在所述硬掩模层上形成包括至少两个线性开口的第二掩模图案，每个所述至少两个线性开口穿过所述相邻列中的所述细长开口并在所述第一方向上延伸; 通过使用第二掩模图案作为蚀刻掩模来蚀刻硬掩模层来形成硬掩模图案; 并通过使用硬掩膜图案蚀刻被蚀刻层。

    Pattern formation method
    4.
    发明申请
    Pattern formation method 审中-公开
    图案形成方法

    公开(公告)号：US20050214694A1

    公开(公告)日：2005-09-29

    申请号：US11010602

    申请日：2004-12-13

    Applicant: Jin Hong ,  Hyun-Woo Kim ,  Myoung-Ho Jung ,  Gyung-Jin Min

    Inventor： Jin Hong ,  Hyun-Woo Kim ,  Myoung-Ho Jung ,  Gyung-Jin Min

    IPC: H01L21/3065 ,  G03F7/00 ,  H01L21/027 ,  H01L21/311 ,  H01L21/314 ,  H01L21/3213 ,  H01L21/768

    CPC classification number: H01L21/31144 ,  H01L21/0273 ,  H01L21/0276 ,  H01L21/3146 ,  H01L21/32139 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76838

    Abstract: A pattern formation method comprises forming a material layer on a substrate, forming an amorphous carbon layer on the material layer, forming an anti-reflective layer on the amorphous carbon layer, forming a silicon photoresist layer on the anti-reflective layer, forming a silicon photoresist layer pattern by patterning the silicon photoresist layer, etching the anti-reflective layer and the amorphous carbon layer using the silicon photoresist layer pattern as an etch mask to form an amorphous carbon layer pattern, and etching the material layer using the amorphous carbon layer pattern as an etch mask to form a pattern in the material layer.

    Abstract translation: 图案形成方法包括在基板上形成材料层，在所述材料层上形成无定形碳层，在所述非晶碳层上形成抗反射层，在所述抗反射层上形成硅光致抗蚀剂层，形成硅 通过图案化硅光致抗蚀剂层，使用硅光致抗蚀剂层图案蚀刻抗反射层和非晶碳层作为蚀刻掩模以形成无定形碳层图案，并使用无定形碳层图案蚀刻材料层， 作为在材料层中形成图案的蚀刻掩模。

    Semiconductor memory device having self-aligned contacts and method of fabricating the same
    5.
    发明授权
    Semiconductor memory device having self-aligned contacts and method of fabricating the same 失效
    具有自对准触点的半导体存储器件及其制造方法

    公开(公告)号：US06885052B2

    公开(公告)日：2005-04-26

    申请号：US09790240

    申请日：2001-02-21

    Applicant: Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

    Inventor： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

    IPC: H01L27/10 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC classification number: H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

    Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

    Abstract translation: 一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。 具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成 其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物 线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准 与第二和第一间隔物。

    Method of fabricating semiconductor device
    7.
    发明申请
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20130005110A1

    公开(公告)日：2013-01-03

    申请号：US13478450

    申请日：2012-05-23

    Applicant: Jun-Ho Yoon ,  Bong-Jin Kuh ,  Ki-Chul Kim ,  Gyung-Jin Min ,  Tae-Jin Park ,  Sang-Ryol Yang ,  Jung-Min Oh ,  Sang-Yoon Woo ,  Young-Sub Yoo ,  Ji-Eun Lee ,  Jong-Sung Lim ,  Yong-Moon Jang ,  Han-Mei Choi ,  Je-Woo Han

    Inventor： Jun-Ho Yoon ,  Bong-Jin Kuh ,  Ki-Chul Kim ,  Gyung-Jin Min ,  Tae-Jin Park ,  Sang-Ryol Yang ,  Jung-Min Oh ,  Sang-Yoon Woo ,  Young-Sub Yoo ,  Ji-Eun Lee ,  Jong-Sung Lim ,  Yong-Moon Jang ,  Han-Mei Choi ,  Je-Woo Han

    IPC: H01L21/02

    CPC classification number: H01L28/90 ,  H01L27/10852

    Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.

    Abstract translation: 提供一种制造具有电容器的半导体器件的方法。 该方法包括形成复合层，包括顺序地堆叠在第一至第n牺牲层和第一至第n支撑层上的交替层上的衬底上。 形成贯穿复合层的多个开口。 在多个开口中形成下电极。 去除第一至第n牺牲层的至少部分以限定在多个开口中相邻的开口和形成在其中的下电极之间延伸的下电极的支撑结构，支撑结构包括第一至第n支撑层和间隙 在第一至第n个支撑层中相邻的第一至第n个牺牲层已被去除之间的区域。 在下电极上形成介电层，在电介质层上形成上电极。

    PLASMA SHIELDING MEMBERS, PLASMA DETECTING STRUCTURES, AND PLASMA REACTION APPARATUSES
    9.
    发明申请
    PLASMA SHIELDING MEMBERS, PLASMA DETECTING STRUCTURES, AND PLASMA REACTION APPARATUSES 审中-公开
    等离子体屏蔽构件，等离子体检测结构和等离子体反应装置

    公开(公告)号：US20150114559A1

    公开(公告)日：2015-04-30

    申请号：US14461651

    申请日：2014-08-18

    Applicant: Eun-Young HAN ,  Hyun-Su JUN ,  Gyung-jin MIN ,  Kye-Hyun BAEK ,  Tae-Rang KIM

    Inventor： Eun-Young HAN ,  Hyun-Su JUN ,  Gyung-jin MIN ,  Kye-Hyun BAEK ,  Tae-Rang KIM

    IPC: C23F1/02 ,  C23C16/04 ,  C23F1/08 ,  H01J37/32

    CPC classification number: H01J37/32495 ,  H01J37/32935 ,  H01J37/32963

    Abstract: A plasma shielding member may include a body having a first surface and a second surface that are opposite to each other, and a plurality of through holes each extending from the first surface to the second surface; a narrower portion of a respective through hole formed at one end of each of the through holes; and/or a wider portion of the respective through hole formed at another end of each of the through holes. A plasma shielding member may include a body including a plurality of through holes that extends from a first surface of the body toward a second surface of the body. Each of the through holes may be defined by a narrower portion of the body at a first end of the respective through hole, and by a wider portion of the body at a second end of the respective through hole.

    Abstract translation: 等离子体屏蔽构件可以包括具有彼此相对的第一表面和第二表面的主体以及从第一表面延伸到第二表面的多个通孔; 每个通孔的一端形成的相应通孔的较窄部分; 和/或形成在每个通孔的另一端的相应通孔的较宽部分。 等离子体屏蔽构件可以包括主体，其包括从主体的第一表面朝向主体的第二表面延伸的多个通孔。 每个通孔可以由相应通孔的第一端处的主体的较窄部分以及在相应通孔的第二端处的主体的较宽部分限定。

    Method of processing semiconductor substrate responsive to a state of chamber contamination
    10.
    发明申请
    Method of processing semiconductor substrate responsive to a state of chamber contamination 审中-公开
    响应室污染状态处理半导体衬底的方法

    公开(公告)号：US20070020780A1

    公开(公告)日：2007-01-25

    申请号：US11370478

    申请日：2006-03-07

    Applicant: Kye-Hyun Baek ,  Chang-Jin Kang ,  Gyung-Jin Min ,  Yong-Jin Kim

    Inventor： Kye-Hyun Baek ,  Chang-Jin Kang ,  Gyung-Jin Min ,  Yong-Jin Kim

    IPC: H01L21/66 ,  G01R31/26

    CPC classification number: H01L22/00

    Abstract: In one embodiment, a method of processing a semiconductor substrate includes measuring a state of a processing chamber contamination before processing each semiconductor substrate. A process condition is then changed responsive to the state of chamber contamination to compensate for an influence of the state of chamber contamination on the process condition. If the change in process condition is outside of predetermined margin, a warning may be generated and the process may be stopped.

    Abstract translation: 在一个实施例中，处理半导体衬底的方法包括在处理每个半导体衬底之前测量处理室污染的状态。 响应于室污染的状态来改变工艺条件以补偿室污染状态对工艺条件的影响。 如果处理条件的改变超出预定余量，则可能产生警告并且可以停止处理。

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