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    Noise equivalent circuit
    1.
    发明授权
    Noise equivalent circuit 有权
    噪声等效电路

    公开(公告)号：US09500689B2

    公开(公告)日：2016-11-22

    申请号：US14237098

    申请日：2012-08-30

    Applicant: Makoto Torigoe ,  Hiroki Funato ,  Takashi Suga ,  Hideki Osaka ,  Yoshiyuki Tsuchie ,  Keisuke Fukumasu ,  Hitoshi Yokota

    Inventor： Makoto Torigoe ,  Hiroki Funato ,  Takashi Suga ,  Hideki Osaka ,  Yoshiyuki Tsuchie ,  Keisuke Fukumasu ,  Hitoshi Yokota

    IPC: G01R29/26 ,  G06F17/50 ,  G01R29/08 ,  G01R31/00 ,  H02M1/44

    CPC classification number: G01R29/26 ,  G01R29/0835 ,  G01R29/0864 ,  G01R31/001 ,  G06F17/5036 ,  G06F2217/82 ,  H02M1/44 ,  Y02T10/82

    Abstract: Provided is a noise equivalent circuit for completing an EMC analysis in a practical time and through a low-cost calculation process at an upstream stage of system design. The noise equivalent circuit includes one or more energy sources; a propagation path for propagation of energy from the energy source including a conductive path such as a cable and an electromagnetic field coupling path due to the coupling of an electric field and a magnetic field with another electronic device or cable; and a GND port connected to a system, and each port is represented by the noise voltage source or the noise current source and the internal impedance. This noise equivalent circuit can determine an external impedance that is varied depending on a load connected externally or the distance from an external device or a cable, whereby the noise of the system as a whole can be analyzed.

    Abstract translation: 提供了一种用于在实际时间内完成EMC分析并通过系统设计上游阶段的低成本计算过程的噪声等效电路。 噪声等效电路包括一个或多个能量源; 由于电场和磁场与另一电子设备或电缆的耦合，包括诸如电缆和电磁场耦合路径的导电路径的能量传播能量的传播路径; 和连接到系统的GND端口，并且每个端口由噪声电压源或噪声电流源和内部阻抗表示。 该噪声等效电路可以确定根据外部连接的负载或与外部设备或电缆的距离而变化的外部阻抗，从而可以分析整个系统的噪声。

    Noise Equivalent Circuit
    2.
    发明申请
    Noise Equivalent Circuit 有权
    噪声等效电路

    公开(公告)号：US20140368217A1

    公开(公告)日：2014-12-18

    申请号：US14237098

    申请日：2012-08-30

    Applicant: Makoto Torigoe ,  Hiroki Funato ,  Takashi Suga ,  Hideki Osaka ,  Yoshiyuki Tsuchie ,  Keisuke Fukumasu ,  Hitoshi Yokota

    Inventor： Makoto Torigoe ,  Hiroki Funato ,  Takashi Suga ,  Hideki Osaka ,  Yoshiyuki Tsuchie ,  Keisuke Fukumasu ,  Hitoshi Yokota

    IPC: G01R29/26 ,  G01R29/08

    CPC classification number: G01R29/26 ,  G01R29/0835 ,  G01R29/0864 ,  G01R31/001 ,  G06F17/5036 ,  G06F2217/82 ,  H02M1/44 ,  Y02T10/82

    Abstract: Provided is a noise equivalent circuit required for completing an EMC analysis in a practical time and through a low-cost calculation process at an upstream stage of system design. According to the present invention, the noise equivalent circuit comprises: one or more energy sources; a propagation path for propagation of energy from the energy source including a conductive path such as a cable and an electromagnetic field coupling path due to the coupling of an electric field and a magnetic field with another electronic device or cable; and a GND port connected to a system, and is characterized in that each port is represented by the noise voltage source or the noise current source and the internal impedance. This noise equivalent circuit can be used to determine an external impedance that is varied depending on a load connected externally or the distance from an external device or a cable, whereby the noise of the system as a whole can be analyzed (see FIG. 1).

    Abstract translation: 提供了在实际的时间内通过在系统设计的上游阶段的低成本计算过程完成EMC分析所需的噪声等效电路。 根据本发明，噪声等效电路包括：一个或多个能量源; 由于电场和磁场与另一电子设备或电缆的耦合，包括诸如电缆和电磁场耦合路径的导电路径的能量传播能量的传播路径; 和连接到系统的GND端口，其特征在于每个端口由噪声电压源或噪声电流源和内部阻抗表示。 该噪声等效电路可用于确定外部阻抗根据外部连接的负载或与外部设备或电缆的距离而变化，从而可以分析整个系统的噪声（参见图1） 。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08878351B2

    公开(公告)日：2014-11-04

    申请号：US12318700

    申请日：2009-01-06

    Applicant: Eiichi Suzuki ,  Hideki Osaka ,  Yutaka Uematsu ,  Yoji Nishio

    Inventor： Eiichi Suzuki ,  Hideki Osaka ,  Yutaka Uematsu ,  Yoji Nishio

    IPC: H01L23/02 ,  H01L23/50 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

    CPC classification number: H01L25/0657 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/18 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15311 ,  H01L2224/05599

    Abstract: A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device.

    Abstract translation: 具有片上芯片结构的半导体器件由第一半导体芯片和偶数对的第二半导体芯片组成，所有第二半导体芯片在中介层的表面上层压在一起。 第一半导体芯片控制每对第二半导体芯片，以激活一个第二半导体芯片，同时使另一个第二半导体芯片失效。 第二半导体芯片以通孔和电极通过凸块彼此相对定位的方式配对在一起。 由于提供有驱动电压（VDD）的驱动电压电极和提供参考电位（VSS）的参考电位电极在成对的第二半导体芯片之间相互连接在一起，因此可以增加每个第二半导体芯片的总静电电容 以便在不增加半导体器件的整体布局面积的情况下显着降低馈送噪声。

    Semiconductor storage device having a plurality of stacked memory chips
    6.
    发明授权
    Semiconductor storage device having a plurality of stacked memory chips 有权
    具有多个层叠的存储芯片的半导体存储装置

    公开(公告)号：US07466577B2

    公开(公告)日：2008-12-16

    申请号：US11392805

    申请日：2006-03-30

    Applicant: Tomonori Sekiguchi ,  Hideki Osaka ,  Tatemi Ido ,  Osamu Nagashima ,  Mitsuaki Katagiri ,  Ichiro Anjo

    Inventor： Tomonori Sekiguchi ,  Hideki Osaka ,  Tatemi Ido ,  Osamu Nagashima ,  Mitsuaki Katagiri ,  Ichiro Anjo

    IPC: G11C5/02 ,  G11C5/06 ,  H01L23/02 ,  H01L23/48

    CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C11/4074 ,  G11C11/4096 ,  H01L24/50

    Abstract: A semiconductor storage employs a base substrate (101) having a command/address external terminal group (CA), a data input/output external terminal group (DQ), and a single chip select external terminal (CS), and also comprises a plurality of memory chips (110) to (113) mounted on a base substrate (101), each of which can individually carry out read and write operations. The terminals (CA), (DQ), and (CS) are connected to an interface chip (120). The interface chip (120) has a chip select signal generation circuit that can individually activate a plurality of memory chips (110) to (113) on the basis of an address signal fed by way of the terminal (CA) and on the basis of a chip select signal fed by way of the terminal (CS).

    Abstract translation: 半导体存储器使用具有命令/地址外部端子组（CA），数据输入/输出外部端子组（DQ）和单个芯片选择外部端子（CS）的基底（101），并且还包括多个 的安装在基板（101）上的存储芯片（110）至（113），每个可独立地进行读写操作。 端子（CA），（DQ）和（CS）连接到接口芯片（120）。 接口芯片（120）具有芯片选择信号生成电路，该电路可以基于通过终端（CA）馈送的地址信号，并基于以下方式单独激活多个存储器芯片（110）〜（113） 通过端子（CS）馈送的芯片选择信号。

    Semiconductor device, memory device and memory module having digital interface
    8.
    发明申请
    Semiconductor device, memory device and memory module having digital interface 失效

    公开(公告)号：US20060018407A1

    公开(公告)日：2006-01-26

    申请号：US10982946

    申请日：2004-11-08

    Applicant: Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    Inventor： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    IPC: H03K9/00

    CPC classification number: H03K5/082 ,  H03K5/135

    Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

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