Abstract:
A circuit and method is provided for determining the delay of an integrated circuit common associated with chip-to-chip variations in the manufacturing process, changes in operating voltage, and fluctuations in temperature. A clock signal is inverted, thus generating an inverted clock signal which is then delayed multiple times, resulting in several delayed versions of the inverted clock signal, with each version being delayed a different length of time. The logical state of each delayed version of the inverted clock signal is then stored. That stored logical state provides an indication as to the magnitude of the delay of the integrated circuit which may then be used to tune critical signals of the integrated circuit to avoid timing problems resulting from variations in IC propagation delay.
Abstract:
In a Teletext transmission system, data is transmitted in digital form during lines in the field blanking period of a composite video signal of a television transmission. On reception, the information is decoded and utilized to provide a display comprising a page having a predetermined number of rows of information in alphanumeric or graphics form. The data is received in blocks comprising information digits and each block has an associated group of address digits so that each block can be directed to an appropriate storage location in a first store, regardless of the order in which the data blocks are transmitted. The contents of the first store can then be transferred in address order into a larger capacity serial store ready for use in generating the display. Thus it is possible for a number of pages of information data to be correctly assembled in serial row order, ready for display generation, in a manner accommodating non-transmitted blank rows.