Abstract:
The architecture, design and fabrication of array of suspended micro-elements with individual seals are described. Read out integrated circuit is integrated monolithically with the suspended elements for low parasitics and high signal to noise ratio detection of changes of their electrical resistance. Array of individually sealed, suspended micro-elements is combined with signal processing chip that contains nonvolatile memory with sensitivity calibration of all elements and interpolation between non-functional elements. When the micro-elements are infrared light absorbers, image analysis and recognition is embedded in the processing chip to form the infrared imaging solution for infrared cameras.
Abstract:
A method for forming an optical deflection device includes providing a semiconductor substrate comprising an upper surface region and a plurality of drive devices within one or more portions of the semiconductor substrate. The upper surface region includes one or more patterned structure regions and at least one open region to expose a portion of the upper surface region to form a resulting surface region. The method also includes forming a planarizing material overlying the resulting surface region to fill the at least one open region and cause formation of an upper planarized layer using the fill material. The method further includes forming a thickness of silicon material at a temperature of less than 300° C. to maintain a state of the planarizing material.
Abstract:
A method for forming an optical deflection device includes providing a semiconductor substrate comprising an upper surface region and a plurality of drive devices within one or more portions of the semiconductor substrate. The upper surface region includes one or more patterned structure regions and at least one open region to expose a portion of the upper surface region to form a resulting surface region. The method also includes forming a planarizing material overlying the resulting surface region to fill the at least one open region and cause formation of an upper planarized layer using the fill material. The method further includes forming a thickness of silicon material at a temperature of less than 300° C. to maintain a state of the planarizing material.
Abstract:
A display system includes a light source and a first optical system coupled to the light source and adapted to provide an illumination beam along an illumination path. The display system also includes a spatial light modulator positioned in the illumination path. The spatial light modulator includes a semiconductor substrate including a plurality of electrode devices and a hinge structure coupled to the semiconductor substrate. The hinge structure includes silicon material. The spatial light modulator also includes a mirror post coupled to the hinge structure and extending to a predetermined distance from the semiconductor substrate and a mirror plate coupled to the mirror post and overlying the plurality of electrode devices. The display system further includes a second optical system coupled to the spatial light modulator and adapted to project an image onto a projection surface.
Abstract:
An optical deflection device for a display application. The optical deflection device includes a semiconductor substrate including an upper surface region and one or more electrode devices provided overlying the upper surface region. The optical deflection device also includes a hinge device including a silicon material and coupled to the upper surface region. The optical deflection device further includes a spacing defined between the upper surface region and the hinge device and a mirror structure including a post portion coupled to the hinge device and a mirror plate portion coupled to the post portion and overlying the hinge device.
Abstract:
Readout integrated circuits placed underneath the suspended sensing elements detect changes of electrical resistance of sensing elements and digitize the signals with digital to analog convertor for each element. Readout electronics provides low parasitics, high signal to noise ratio, high data rate, high dynamic range and instantaneous global readout.
Abstract:
Readout integrated circuits placed below the suspended sensor elements detect changes of electrical resistance of sensor elements and digitize the signals with digital to analog convertor for each element. Readout electronics provides low parasitics, high signal to noise ratio, high data rate, high dynamic range and instantaneous global readout.
Abstract:
A method for forming an optical deflection device includes providing a semiconductor substrate comprising an upper surface region and a plurality of drive devices within one or more portions of the semiconductor substrate. The upper surface region includes one or more patterned structure regions and at least one open region to expose a portion of the upper surface region to form a resulting surface region. The method also includes forming a planarizing material overlying the resulting surface region to fill the at least one open region and cause formation of an upper planarized layer using the fill material. The method further includes forming a thickness of silicon material at a temperature of less than 300° C. to maintain a state of the planarizing material.
Abstract:
The architecture, design and fabrication of array of suspended micro-elements with individual seals are described. Read out integrated circuit is integrated monolithically with the suspended elements for low parasitics and high signal to noise ratio detection of changes of their electrical resistance. Array of individually sealed, suspended micro-elements is combined with signal processing chip that contains nonvolatile memory with sensitivity calibration of all elements and interpolation between non-functional elements. When the micro-elements are infrared light absorbers, image analysis and recognition is embedded in the processing chip to form the infrared imaging solution for infrared cameras.
Abstract:
A method for forming an optical deflection device includes providing a semiconductor substrate comprising an upper surface region and a plurality of drive devices within one or more portions of the semiconductor substrate. The upper surface region includes one or more patterned structure regions and at least one open region to expose a portion of the upper surface region to form a resulting surface region. The method also includes forming a planarizing material overlying the resulting surface region to fill the at least one open region and cause formation of an upper planarized layer using the fill material. The method further includes forming a thickness of silicon material at a temperature of less than 300° C. to maintain a state of the planarizing material.