Abstract:
A photolithography system for printing a pattern of at least one contact or via on a wafer is provided. The system comprises a reticle having a layout, the layout comprises at least one polygon-shaped hole, wherein the at least one polygon-shaped hole comprises at least eight sides.
Abstract:
An image reversal method is described that removes the etch resistance requirement from a resist. A high resolution resist pattern comprised of islands, lines, or trenches is formed with a large process window by exposing through one or more masks including phase edge masks and optionally with resolution enhancement techniques. A complementary material replacement (CMR) layer comprised of an organic polymer or material such as fluorosilicate glass which has a lower etch rate than the resist is coated over the resist pattern. CMR and resist layers are etched simultaneously to provide an image reversed pattern in the CMR layer which is etch transferred into a substrate. The method avoids edge roughness like bird's beak defects in the etched pattern and is useful for applications including forming contact holes in dielectric layers, forming polysilicon gates, and forming trenches in a damascene process. It is also valuable for direct write methods where an image reversal scheme is desired.
Abstract:
A new and improved method for measuring dimensions of a photoresist pattern profile on a wafer substrate during photolithography for the fabrication of integrated circuits on the substrate. According to one embodiment, the method includes fixing the photoresist pattern profile on the substrate using a spin-on glass (SOG) procedure. In another embodiment, the method includes fixing the photoresist pattern profile on the substrate using a sputter oxide (SO) procedure. The fixed photoresist pattern is then subjected to a microscopy procedure, typically transmission electron microscopy (TEM), to measure the exact linewidth and other dimensions of the profile. The method prevents distortion of the profile during fixation and facilitates an accurate determination of the profile dimensions.
Abstract:
A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.
Abstract:
A phase shifting mask set and method of using the phase shifting mask set to pattern a layer of negative photoresist. The mask set comprises a first phase shifting mask and a second phase shifting mask. The first and second phase shifting masks have regions of 90° phase shift and −90° phase shift in the contact hole regions of the masks. In the second phase shift mask the phase shift regions are rotated 90° spatially with respect to the phase shift regions of the first phase shift mask. A layer of negative photoresist is exposed with the first and second phase shift masks and developed to form the photoresist pattern used to form contact holes.
Abstract:
A method of forming an alternative phase shifting mask and forming a circuit pattern on a wafer using the mask are described. Optical proximity correction is added to a data file, in which a description of a circuit pattern has been stored, to obtain a first modified data file. The first modified data file is then separated into a second modified data file, for regions of the mask having dense line/space patterns, and a third modified data file, for regions of the mask having isolated line space patterns. Critical dimension bias is then added to the second modified data file forming a fourth modified data file. The third modified data file and the fourth modified data file are then merged into a single fifth modified data file. The fifth modified data file is then is then converted to an alternative phase shift data file. An alternative phase shift mask is then formed from the alternative phase shift data file. The alternative phase shift mask has then been corrected for optical proximity effect and critical dimension bias has been added. This alternative phase shift mask can then be used in forming the circuit pattern on an integrated circuit wafer.
Abstract:
The present invention provides an anti-reflection film for lithographic application on tungsten-silicide containing substrate. In one embodiment of the present invention, a structure for improving lithography patterning in integrated circuit comprises a tungsten-silicide layer, a diaphanous layer located above the tungsten-silicide layer, an anti-reflection layer located above the diaphanous layer, and a photoresist layer located above the anti-reflection layer for patterning the integrated circuit pattern.
Abstract:
A method for improving the patterning process of a conductive layer using a dual-layer cap of oxynitride and silicon nitride. The oxynitride layer acts as a BARC (Bottom Anti-Reflective Coating) to improve photolithography process performance. The oxynitride is formed by plasma-enhanced chemical vapor deposition.
Abstract:
A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.
Abstract:
A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.