公开(公告)号：US08372755B2

公开(公告)日：2013-02-12

申请号：US12686866

申请日：2010-01-13

Applicant: Shiang-Bau Wang ,  Hun-Jan Tao

Inventor： Shiang-Bau Wang ,  Hun-Jan Tao

IPC: H01L21/302 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of film stacks, each film stack having a silicon oxide layer and a carbon-containing material layer, each film stack having a thickness equal to or less than about 10 angstrom; patterning the multi-layer hard mask layer, forming an opening of the multi-hard mask layer; etching the gate material layers within the opening of the multi-layer hard mask layer, forming a gate structure; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein a first remaining thickness of the multi-layer hard mask layer is less than a first thickness; and thereafter performing an epitaxy growth to the semiconductor substrate, wherein a second remaining thickness of the multi-layer hard mask layer is greater than a second thickness.

Abstract translation: 公开了一种制造半导体器件的方法。 在一个实施例中，该方法可以包括提供半导体衬底; 在所述半导体衬底上形成栅极材料层; 在所述栅极材料层上形成多层硬掩模层，其中所述多层硬掩模层包括多个膜堆叠，每个膜堆叠具有氧化硅层和含碳材料层，每个膜堆叠具有 厚度等于或小于约10埃; 图案化多层硬掩模层，形成多硬掩模层的开口; 蚀刻多层硬掩模层的开口内的栅极材料层，形成栅极结构; 对所述半导体衬底进行倾斜角度离子注入工艺，其中所述多层硬掩模层的第一剩余厚度小于第一厚度; 然后对所述半导体衬底进行外延生长，其中所述多层硬掩模层的第二剩余厚度大于第二厚度。

公开(公告)号：US07875547B2

公开(公告)日：2011-01-25

申请号：US11035325

申请日：2005-01-12

Applicant: Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Peng-Fu Hsu ,  Hun-Jan Tao

Inventor： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Peng-Fu Hsu ,  Hun-Jan Tao

IPC: H01L21/4763

CPC classification number: H01L21/76802 ,  H01L21/76835

Abstract: Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.

Abstract translation: 公开了形成接触孔结构的方法和结构。 这些方法首先在衬底上形成基本上无硅的材料层。 在基本无硅材料层上形成材料层。 在基本无硅的材料层和材料层内形成接触孔，而基本上不损坏衬底。 此外，在接触孔中形成导电层以形成接触结构。

公开(公告)号：US20100190349A1

公开(公告)日：2010-07-29

申请号：US12798201

申请日：2010-03-30

Applicant: Huang-Ming Chen ,  Chun-Li Chou ,  Chao-Cheng Chen ,  Hun-Jan Tao

Inventor： Huang-Ming Chen ,  Chun-Li Chou ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC: H01L21/465 ,  C23F1/00

CPC classification number: H01L21/68735 ,  H01J37/3244 ,  H01J37/32642 ,  H01L21/02046 ,  H01L21/31116 ,  H01L21/67069 ,  Y10S156/914 ,  Y10S156/915 ,  Y10T279/23

Abstract: A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck.

Abstract translation: 防止在半导体衬底的背面形成污染性聚合物膜的方法包括提供在蚀刻操作期间释放氧气的氧浸渍聚焦环和/或氧浸渍卡盘。 该方法还通过在冷却气体混合物中混合氧将氧气输送到衬底，在蚀刻和清洁衬底期间将聚焦环保持在不高于衬底温度的温度，使用包括悬浮衬底的两步骤等离子体清洗序列 在卡盘上方

公开(公告)号：US07629275B2

公开(公告)日：2009-12-08

申请号：US11698239

申请日：2007-01-25

Applicant: Jennifer Chen ,  Chi-Chun Chen ,  Hun-Jan Tao

Inventor： Jennifer Chen ,  Chi-Chun Chen ,  Hun-Jan Tao

IPC: H01L21/00

CPC classification number: H01L21/324 ,  H01L21/26513 ,  H01L21/2686 ,  H01L29/6659

Abstract: A method of forming an integrated circuit is provided. The method includes performing a multiple-time flash anneal process to a wafer, wherein the multiple-time flash anneal process comprises preheating the wafer to a first preheat temperature; performing a first flash on the wafer with a first flash energy; preheating the wafer to a second preheat temperature; and performing a second flash on the wafer with a second flash energy.

Abstract translation: 提供一种形成集成电路的方法。 该方法包括对晶片执行多次闪光退火处理，其中多次闪光退火工艺包括将晶片预热至第一预热温度; 以第一闪光能量在晶片上进行第一次闪光; 将晶片预热至第二预热温度; 以及以第二闪光能量在所述晶片上执行第二次闪光。

公开(公告)号：US07531399B2

公开(公告)日：2009-05-12

申请号：US11532308

申请日：2006-09-15

Applicant: Fong-Yu Yen ,  Cheng-Lung Hung ,  Peng-Fu Hsu ,  Vencent S. Chang ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

Inventor： Fong-Yu Yen ,  Cheng-Lung Hung ,  Peng-Fu Hsu ,  Vencent S. Chang ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

IPC: H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/518

Abstract: A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.

Abstract translation: 公开了一种半导体器件，包括：衬底; 第一高k电介质层; 由不同的高k材料形成的第二高k电介质层; 和金属门。 在另一种形式中，公开了一种形成半导体器件的方法，包括：提供衬底; 在所述衬底上形成第一高k电介质层; 在所述第一介电层上形成不同高k材料的第二电介质层; 以及在所述第二电介质层上形成栅极结构。 在另一种形式中，公开了一种形成半导体器件的方法，其包括：提供衬底; 在基底上形成界面层; 在界面层上形成第一高k电介质层; 进行氮化技术; 进行退火; 在所述第一介电层上形成不同高k材料的第二高k电介质层; 以及在所述第二电介质层上方形成金属栅极结构。

公开(公告)号：US20080308899A1

公开(公告)日：2008-12-18

申请号：US11763566

申请日：2007-06-15

Applicant: Yu-Lien Huang ,  Yi-Chen Huang ,  Jim Cy Huang ,  Weng Chang ,  Hun-Jan Tao

Inventor： Yu-Lien Huang ,  Yi-Chen Huang ,  Jim Cy Huang ,  Weng Chang ,  Hun-Jan Tao

IPC: H01L29/06 ,  H01L29/00

CPC classification number: H01L21/823425 ,  H01L21/823468 ,  Y10S438/981

Abstract: Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.

Abstract translation: 提供了包括基板的半导体器件。 形成在基板上的栅极。 门包括侧壁。 在衬底上形成并且邻近门的侧壁的间隔物。 间隔件具有基本上三角形的几何形状。 在第一栅极和第一间隔物上形成接触蚀刻停止层（CESL）。 CESL的厚度与第一间隔件的宽度在大约0.625和16之间。

公开(公告)号：US07436009B2

公开(公告)日：2008-10-14

申请号：US11732883

申请日：2007-04-04

Applicant: Yi-Chen Huang ,  Chien-Chung Fu ,  Ming-Hong Hsieh ,  Hui Ouyang ,  Yi-Nien Su ,  Hun-Jan Tao

Inventor： Yi-Chen Huang ,  Chien-Chung Fu ,  Ming-Hong Hsieh ,  Hui Ouyang ,  Yi-Nien Su ,  Hun-Jan Tao

IPC: H01L29/06

CPC classification number: H01L21/76865 ,  H01L21/76808 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76862

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the surface of the first conductive layer. A trench structure is formed on the via structure in the dielectric without the conductive liner layer in the trench.

Abstract translation: 公开了通孔和沟槽结构和制造方法。 该结构包括电介质层中的导电层，以及介电层中与导电层表面的一部分接触的通孔结构。 通孔结构包括与第一导电层的表面的部分接触的导电衬垫。 在电介质中的通孔结构上形成沟槽结构，而沟槽中没有导电衬垫层。

公开(公告)号：US20080242108A1

公开(公告)日：2008-10-02

申请号：US11730551

申请日：2007-04-02

Applicant: Weng Chang ,  Fong-Yu Yen ,  Hun-Jan Tao ,  Mong-Song Liang

Inventor： Weng Chang ,  Fong-Yu Yen ,  Hun-Jan Tao ,  Mong-Song Liang

IPC: H01L21/46

CPC classification number: H01L21/28079 ,  H01L21/28088 ,  H01L21/67207

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber.

Abstract translation: 公开了一种制造半导体器件的方法。 该方法包括提供第一室和第二室。 第一室和第二室通过压力差单元连接，用于在第一室中的基板上沉积金属膜，经由压差单元将衬底转移到第二室，而不将衬底暴露于周围环境;以及 在第二室中的金属膜上沉积含硅膜。

公开(公告)号：US20080138983A1

公开(公告)日：2008-06-12

申请号：US11634303

申请日：2006-12-06

Applicant: Hao-Ming Lien ,  Jim Cy Huang ,  Donald Y. Chao ,  Ling-Yen Yeh ,  Hun-Jan Tao

Inventor： Hao-Ming Lien ,  Jim Cy Huang ,  Donald Y. Chao ,  Ling-Yen Yeh ,  Hun-Jan Tao

IPC: H01L21/44

CPC classification number: H01L21/76832 ,  H01L21/2686 ,  H01L21/76825 ,  H01L21/76828 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method of forming tensile stress films for NFET Performance enhancement, comprising the steps of: (a) providing a semiconductor substrate having a gate structure patterned thereon; (b) performing a deposition process to form a first dielectric film overlying the semiconductor substrate and covering the gate structure; (c) performing a curing process on the first dielectric film; (d) successively repeating the step (b) of deposition process and the step (c) of curing process at least once to form at least one second dielectric film on the first dielectric film until the total thickness of the first dielectric film and the at least one second dielectric film reaches a target thickness.

Abstract translation: 一种形成用于NFET性能增强的拉伸应力膜的方法，包括以下步骤：（a）提供在其上图案化的栅极结构的半导体衬底; （b）进行沉积工艺以形成覆盖半导体衬底并覆盖栅极结构的第一电介质膜; （c）对所述第一电介质膜进行固化处理; （d）连续重复沉积处理步骤（b）和固化过程的步骤（c）至少一次，以在第一介电膜上形成至少一个第二电介质膜，直到第一介电膜和第 至少一个第二介电膜达到目标厚度。

公开(公告)号：US07378713B2

公开(公告)日：2008-05-27

申请号：US11552704

申请日：2006-10-25

Applicant: Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

Inventor： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

IPC: H01L27/092 ,  H01L29/423

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

Abstract: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.

Abstract translation: 具有双金属栅极结构的半导体器件及其制造方法。 提供了具有由绝缘层分隔开的第一掺杂区域和第二掺杂区域的半导体衬底。 在第一掺杂区上形成第一金属栅叠层，在第二掺杂区上形成第二金属栅叠层。 密封层设置在第一栅极堆叠和第二栅极叠层的侧壁上。 第一金属栅叠层包括界面层，界面层上的高k电介质层，高k电介质层上的第一金属层，第一金属层上的金属插入层，金属上的第二金属层 插入层和第二金属层上的多晶硅层。 第二金属栅堆叠包括界面层，界面层上的高k电介质层，高k电介质层上的第二金属层和第二金属层上的多晶硅层。