公开(公告)号：US20250157988A1

公开(公告)日：2025-05-15

申请号：US18509751

申请日：2023-11-15

Applicant: Infineon Technologies AG

Inventor： Hans Taddiken ,  Christoph Kadow ,  Anton Steltenpohl

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00

Abstract: A three-dimensional integrated circuit includes a first integrated circuit having a first transistor and a first buried oxide layer; a second integrated circuit having a second transistor and a second buried oxide layer; a bond interface between an upper surface of the first integrated circuit and an upper surface of the second integrated circuit; a passivation layer coupled to the first buried oxide layer; and a mold wafer coupled to the second buried oxide layer.

公开(公告)号：US12302594B2

公开(公告)日：2025-05-13

申请号：US17954830

申请日：2022-09-28

Applicant: Infineon Technologies AG

Inventor： Alim Karmous ,  Thorsten Arnold

IPC: H10D12/00 ,  H10D30/01 ,  H10D62/10 ,  H10D64/27

Abstract: A power semiconductor device includes an active region with power cells, each configured to conduct a load current portion between first and second load terminals. Each power cell includes: trenches and mesas laterally confined by the trenches and in a vertical direction adjoining a drift region. The mesas include an active mesa having a source region of a first conductivity type and a body region of a second conductivity type separating the source region from the drift region. Both the source and body region are electrically connected to the first load terminal. At least one trench adjacent to the active mesa is configured to induce a conductive channel in the active mesa. A punch through structure s electrically separated from the active mesa by at least one separation stack.

公开(公告)号：US12301218B2

公开(公告)日：2025-05-13

申请号：US18325875

申请日：2023-05-30

Applicant: Infineon Technologies AG

Inventor： Semen Syroiezhin ,  Valentyn Solomko ,  Matthias Voelkel ,  Aleksey Zolotarevskyi

IPC: H03K17/04 ,  H03K17/0412 ,  H03K17/042 ,  H03K17/16 ,  H03K17/687 ,  H03K17/693

Abstract: A radio frequency (RF) switch includes a switchable RF path including a plurality of transistors coupled in series; a gate bias network including a plurality of resistors, wherein the gate bias network is coupled to each of the plurality of transistors in the switchable RF path; and a bypass network including a first plurality of transistors coupled in parallel to each of the plurality of transistors in the switchable RF path and a second plurality of transistors coupled in parallel to each of the plurality of resistors in the gate bias network.

公开(公告)号：US12301216B2

公开(公告)日：2025-05-13

申请号：US18463680

申请日：2023-09-08

Applicant: Infineon Technologies AG

Inventor： Valentyn Solomko ,  Semen Syroiezhin

IPC: H03K17/041 ,  H03K17/081

Abstract: An RF switch arrangement includes a shunt switch having a first RF terminal, a second RF terminal coupled to ground, a main control input, and an acceleration control input; a series switch having a first RF terminal coupled to the first RF terminal of the shunt switch, a second RF terminal, a main control input, and an acceleration control input; and a switching time acceleration circuit having a positive acceleration path input, a negative acceleration path input, and a first output coupled to the main control input of the series switch.

公开(公告)号：US12294638B2

公开(公告)日：2025-05-06

申请号：US18359065

申请日：2023-07-26

Applicant: Infineon Technologies AG

Inventor： Andreas Schwarz ,  Thomas Josef Bauernfeind ,  Stefan Schmalzl ,  Thomas Obermueller ,  Martin Louda ,  Furqan Farooq Fazili

IPC: H04L7/00 ,  H04L7/033

Abstract: A method for monitoring an RF receiver includes generating of a digital test signal based on a signal, wherein the digital test signal includes a stream of digital test samples having a digital test sample; generating a monitoring signal based on the digital test signal; and coupling of the monitoring signal into a receiver path. The monitoring signal is processed in the receiver path to generate a processed monitoring signal and a stream of digital monitoring samples representing the processed monitoring signal. Information is determined indicating at least one property related to the receiver path based on a processing of a set of digital monitoring samples of the stream of digital monitoring samples. The set of digital monitoring samples includes a digital monitoring sample. The method further includes controlling the RF receiver such that the digital monitoring sample is generated a predetermined time duration after generating the digital test sample.

公开(公告)号：US12292531B2

公开(公告)日：2025-05-06

申请号：US18390361

申请日：2023-12-20

Applicant: Infineon Technologies AG

Inventor： Dian Tresna Nugraha ,  Markus Bichl ,  Dyson Wilkes

IPC: G01S7/40 ,  G01S7/02 ,  G01S7/292

Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.

公开(公告)号：US20250141834A1

公开(公告)日：2025-05-01

申请号：US18886745

申请日：2024-09-16

Applicant: Infineon Technologies AG

Inventor： Martin Barth ,  Markus Matzberger ,  Tobias Otter

IPC: H04L61/50

Abstract: A method for assigning an address to an electronic device is described. The method may comprise starting a test system for performing a test of a circuit arrangement comprising the electronic device, and implementing a communication protocol between the circuit arrangement and the test system. The method may also comprise reading out a predetermined unique identifier (UID) of the electronic device by using the test system, assigning the UID to at least one property of the electronic device within a lookup table, wherein the property is determined by using the test system, and assigning an address to the electronic device by using the lookup table.

公开(公告)号：US12288727B2

公开(公告)日：2025-04-29

申请号：US18130662

申请日：2023-04-04

Applicant: Infineon Technologies AG

Inventor： Edmund Riedl ,  Steffen Jordan ,  Stefan Miethaner ,  Stefan Schwab

IPC: H01L23/29 ,  H01L21/56

Abstract: A method of manufacturing a package includes forming an adhesion promoter on at least part of an electronic component. The adhesion promoter is a morphological adhesion promoter including a morphological structure having a plurality of openings. The method further includes at least partially encapsulating the electronic component with an inorganic encapsulant with the adhesion promoter in between. The adhesion promoter enhances adhesion between at least part of the electronic component and the encapsulant.

公开(公告)号：US12287862B2

公开(公告)日：2025-04-29

申请号：US17981583

申请日：2022-11-07

Applicant: Infineon Technologies AG

Inventor： Sandeep Vangipuram ,  Glenn Farrall ,  Albrecht Mayer ,  Frank Hellwig

IPC: G06F21/44 ,  G06F21/60 ,  G06F21/62 ,  G06F21/71 ,  G06F21/78

Abstract: A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.

公开(公告)号：US20250130294A1

公开(公告)日：2025-04-24

申请号：US18916926

申请日：2024-10-16

Applicant: Infineon Technologies AG

Inventor： Horst THEUSS

IPC: G01R33/00 ,  G01R33/09

Abstract: A sensor device contains a magnetic field sensor chip. The magnetic field sensor chip contains a semiconductor substrate having a first surface and a second surface opposite the first surface, a sensor element that is arranged at the first surface and is configured to detect a magnetic field present at the location of the sensor element, and at least one trench extending from at least one of the two surfaces into the semiconductor substrate. The sensor element is spaced laterally from the at least one trench.