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公开(公告)号：US20050225955A1
公开(公告)日：2005-10-13
申请号：US10821458
申请日：2004-04-09
Applicant: John Grebenkemper , Frank Mikalauskas , Srinivasan Venkataraman , Jonathan Buck
Inventor： John Grebenkemper , Frank Mikalauskas , Srinivasan Venkataraman , Jonathan Buck
CPC classification number: H05K1/0218 , H05K1/0298 , H05K2201/0723 , H05K2201/09309 , H05K2201/09327
Abstract: A printed circuit board includes a power plane and a ground reference plane that includes two opposite sides. The power plane is positioned proximate one side of the ground reference plane. A signal layer is positioned proximate the other side of the ground reference plane to isolate the power plane from the signal layer. Any noise on the power plane or the signal layer is thus isolated by the intervening ground plane.
Abstract translation: 印刷电路板包括电源平面和包括两个相对侧的接地参考平面。 电源平面位于接地参考平面的一侧。 信号层位于接地参考平面的另一侧附近，以将功率平面与信号层隔离。 电力平面或信号层上的任何噪声因此被插入的接地层隔离。
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2.发明授权公开(公告)号：US06366972B1
公开(公告)日：2002-04-02
申请号：US08685256
申请日：1996-07-23
Applicant: C. John Grebenkemper , Dong Nguyen
Inventor： C. John Grebenkemper , Dong Nguyen
IPC: G06F1300
CPC classification number: G06F13/4086
Abstract: A multi-user bus is divided into a number of bus portions, one for each user. Each bus portion is coupled, at one end, to one of the multiple users and through an impedance matching network to the other bus portions in a star configuration. The disclosed embodiment teaches various resistive impedance matching networks.
Abstract translation: 多用户总线被分成多个总线部分，每个用户一个。 每个总线部分在一端耦合到多个用户中的一个并且通过与星形配置中的其它总线部分的阻抗匹配网络相耦合。 所公开的实施例教导了各种电阻阻抗匹配网络。
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公开(公告)号：US5958034A
公开(公告)日：1999-09-28
申请号：US935038
申请日：1997-09-22
Applicant: Jack An-Kou Shiao , C. John Grebenkemper , Frank Mikalauskas
Inventor： Jack An-Kou Shiao , C. John Grebenkemper , Frank Mikalauskas
CPC classification number: G06F13/409
Abstract: A method for manufacturing a bus having enhanced signals qualities which includes the steps of determining the intrinsic inductance per unit length (L.sub.0) and intrinsic capacitance per unit length (C.sub.0) of the unloaded bus. The method also includes the step of determining the load capacitance per unit length (C.sub.d) of the bus that is attributable to the peripheral devices that will be attached to the bus. Based on these values, an adjustment inductance (L.sub.d) per unit length for the bus is calculated for the bus with L.sub.d being substantially equal to L.sub.0 * C.sub.d /C.sub.0. Finally, one inductor of value L.sub.d is added per unit length of the bus. The added adjustment inductance offsets the capacitance attributable to the peripheral devices attached to the bus. The result is that signals within the bus have rise and fall times acceptable for high speed operation.
Abstract translation: 一种用于制造具有增强的信号质量的总线的方法，其包括以下步骤：确定每单位长度的固有电感（L0）和无负载总线的每单位长度（C0）的固有电容。 该方法还包括确定归因于将要连接到总线的外围设备的总线的每单位长度（Cd）的负载电容的步骤。 基于这些值，对于总线，计算总线的单位长度的调整电感（Ld），其中Ld基本上等于L0 * Cd / C0。 最后，在总线的每单位长度上增加一个值为Ld的电感器。 附加的调整电感抵消了归因于连接到总线的外围设备的电容。 结果是总线中的信号具有高速运行可接受的上升和下降时间。
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公开(公告)号：US06873219B2
公开(公告)日：2005-03-29
申请号：US10352753
申请日：2003-01-28
Applicant: John Grebenkemper
Inventor： John Grebenkemper
CPC classification number: H05K1/0234 , H05K1/167 , H05K2201/0355 , H05K2201/09309 , H05K2203/0723
Abstract: A method and related configuration for attenuating high-frequency noise that may appear on power planes in printed circuit boards. In one embodiment, the noise attenuation means of the present invention involves applying a lower conductivity material between the conductive and dielectric layers within a printed circuit board. High-frequency noise is then attenuated by the skin effect. In another embodiment, the low conductivity material is applied between the power plane and dielectric layer within the printed circuit board. The low conductivity material may be a material, such as nickel or lead, having an electrical conductivity ranging between about 1×104 mhos/m and 5.8×107 mhos/m for layers having a thickness of about 2 mils.
Abstract translation: 一种用于衰减印刷电路板电源平面上可能出现的高频噪声的方法和相关配置。 在一个实施例中，本发明的噪声衰减装置包括在印刷电路板内的导电层和介电层之间施加较低导电性的材料。 然后，高频噪声被皮肤效应衰减。 在另一个实施例中，低电导率材料被施加在印刷电路板内的电源平面和电介质层之间。 对于具有约2密耳厚度的层，低导电性材料可以是诸如镍或铅的材料，对于具有约2密耳厚度的层，其电导率范围在约1×10 4 mhos / m至5.8×10 7 mhos / m之间。
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Patent Agency Ranking
公开(公告)号：US5371417A
公开(公告)日：1994-12-06
申请号：US87556
申请日：1993-07-02
Applicant: Russell N. Mirov , Duc N. Le , Frank Mikalauskas , C. John Grebenkemper , Kinying Kwan
Inventor： Russell N. Mirov , Duc N. Le , Frank Mikalauskas , C. John Grebenkemper , Kinying Kwan
CPC classification number: G06F11/1604 , G06F1/06 , H03L7/00 , G06F11/1608
Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.
Abstract translation: 用于产生用于分配到多个同步时钟的装置的多个多频数字时钟信号的时钟发生器系统包括两个分离的基本相同的结构的时钟发生器单元，其以锁定步骤一致地操作。 一个发生器单元的数字时钟信号输出被分配到同步时钟的装置和误差检测电路，该电路也接收来自其他时钟发生器单元的数字时钟信号，用于彼此比较。 在检测到错误的情况下，错误检测电路将产生一个错误信号，以停止使用时钟发生器系统的系统的操作，并复位时钟发生器。
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6.发明授权Method and apparatus to attenuate power plane noise on a printed circuit board using high ESR capacitors 有权使用高ESR电容衰减印刷电路板上的电源平面噪声的方法和装置公开(公告)号：US06870436B2
公开(公告)日：2005-03-22
申请号：US10097215
申请日：2002-03-11
Applicant: John Grebenkemper
Inventor： John Grebenkemper
CPC classification number: H05K1/0234 , G06F17/5036 , H05K1/0231 , H05K3/0005 , H05K9/0039 , H05K2201/09309
Abstract: In a method of the present invention, performance characteristics of a printed circuit board are analyzed. The printed circuit board, bypass components and an applied stimulus are modeled. Each of the bypass components includes a capacitor and a resistor in series with each other. Alternatively, a second capacitor is coupled in parallel to the above capacitor and resistor. A simulation of the circuit model is then performed. In this embodiment of the invention, the simulation is responsive to the stimulus as is performed over a range of bypass resistor values. In another embodiment of the invention, a printed circuit board is described with components and characteristics that reduce noise. Such a printed circuit board includes a power plane and a plurality of bypass components. Moreover, the plurality of bypass components include bypass capacitors and bypass resistors coupled in series between the positive power plane and the negative power plane.
Abstract translation: 在本发明的方法中，分析印刷电路板的性能特征。 印刷电路板，旁路部件和应用的刺激被建模。 每个旁通部件包括彼此串联的电容器和电阻器。 或者，第二电容器并联到上述电容器和电阻器。 然后进行电路模型的模拟。 在本发明的该实施例中，模拟响应于在一定范围的旁路电阻值上执行的激励。 在本发明的另一个实施例中，描述了一种降低噪声的部件和特性的印刷电路板。 这种印刷电路板包括电源平面和多个旁路部件。 此外，多个旁路部件包括串联耦合在正电源平面和负电源平面之间的旁路电容器和旁路电阻器。
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公开(公告)号：US5539328A
公开(公告)日：1996-07-23
申请号：US449450
申请日：1995-05-24
Applicant: Russell N. Mirov , Duc N. Le , Frank Mikalauskas , C. John Grebenkemper , Kinying Kwan
Inventor： Russell N. Mirov , Duc N. Le , Frank Mikalauskas , C. John Grebenkemper , Kinying Kwan
CPC classification number: G06F11/1604 , G06F1/06 , H03L7/00 , G06F11/1608
Abstract: To minimize skew and jitter imposed upon signals communicated along a printed circuit signal path a termination circuit is formed proximate the sink or receiving element of the signals. The termination circuit can be resistive, coupling the signal path to a supply power and to a ground potential.
Abstract translation: 为了最小化沿着印刷电路信号路径传送的信号施加的偏斜和抖动，在信号的信宿或接收元件附近形成终端电路。 终端电路可以是电阻性的，将信号路径耦合到电源和接地电位。
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公开(公告)号：US5491442A
公开(公告)日：1996-02-13
申请号：US442851
申请日：1995-05-17
Applicant: Russell N. Mirov , Duc N. Le , Frank Mikalauskas , C. John Grebenkemper , Kinying Kwan
Inventor： Russell N. Mirov , Duc N. Le , Frank Mikalauskas , C. John Grebenkemper , Kinying Kwan
CPC classification number: G06F11/1604 , G06F1/06 , H03L7/00 , G06F11/1608
Abstract: A clock generator produces a plurality of clock signals from a master clock and a delayed clock version of the master clock by applying a division of the delayed version of the master clock to the data input of a flip-flop and clocking the flip-flop with the master clock. A number of plurality of clock signals are produced by applying the output of the flip-flop to the data input of an array of second flip-flops--one flip-flop of the array for each of the number of clock signals--that are clocked by the delayed version of the master clock.
Abstract translation: 时钟发生器通过将主时钟的延迟版本的分割应用于触发器的数据输入并对触发器进行计时，从主时钟和主时钟的延迟时钟版本产生多个时钟信号， 主时钟。 通过将触发器的输出施加到第二触发器阵列的数据输入（多个时钟信号中的每一个的阵列的一个触发器）中产生多个时钟信号，这些触发器被计时 通过主时钟的延迟版本。
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公开(公告)号：US5461332A
公开(公告)日：1995-10-24
申请号：US289823
申请日：1994-10-03
Applicant: Russell N. Mirov , Duc N. Le , Frank Mikalauskas , C. John Grebenkemper , Kinying Kwan
Inventor： Russell N. Mirov , Duc N. Le , Frank Mikalauskas , C. John Grebenkemper , Kinying Kwan
CPC classification number: G06F11/1604 , G06F1/06 , H03L7/00 , G06F11/1608
Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.
Abstract translation: 用于产生用于分配到多个同步时钟的装置的多个多频数字时钟信号的时钟发生器系统包括两个分离的基本相同的结构的时钟发生器单元，其以锁定步骤一致地操作。 一个发生器单元的数字时钟信号输出被分配到同步时钟的装置和误差检测电路，该电路也接收来自其他时钟发生器单元的数字时钟信号，用于彼此比较。 在检测到错误的情况下，错误检测电路将产生一个错误信号，以停止使用时钟发生器系统的系统的操作，并复位时钟发生器。
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