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公开(公告)号：US07423073B2
公开(公告)日：2008-09-09
申请号：US10995806
申请日：2004-11-23
Applicant: James M. Mrvos , Girish S. Patil , Karthik Vaideeswaran
Inventor： James M. Mrvos , Girish S. Patil , Karthik Vaideeswaran
CPC classification number: C08G59/68 , B41J2/1603 , B41J2/1637 , C08L63/00 , G03F7/038
Abstract: A radiation curable resin composition having improved flexibility. The radiation curable composition having from about 5 to about 50 weight percent of a difunctional polymeric compound; from about 1 to about 10 weight percent of a photoinitiator; from about 1 to about 10 weight percent of a flexibilizer agent, wherein the flexibilizer agent has a molecular weight ranging from about 400 to about 10,000; and about 30 to about 90 weight percent of the non-photoreactive solvent, wherein the weight percents are based on the total weight of the resin composition. Ink jet print heads and ink jet printing apparatusess comprising ink jet print heads utilizing the radiation curable resin compositions are also included.
Abstract translation: 一种具有改善柔性的辐射固化树脂组合物。 所述可辐射固化组合物具有约5至约50重量％的双官能聚合物; 约1至约10重量％的光引发剂; 约1至约10重量％的增韧剂，其中所述增韧剂的分子量范围为约400至约10,000; 和约30至约90重量％的非光反应性溶剂，其中重量百分比基于树脂组合物的总重量。 还包括使用该辐射固化树脂组合物的喷墨打印头和喷墨打印设备，包括喷墨打印头。
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公开(公告)号：US20070259292A1
公开(公告)日：2007-11-08
申请号：US11780234
申请日：2007-07-19
Applicant: John Krawczyk , James Mrvos , Girish Patil , Jason Vanderpool , Brian Hart , Christopher Money , Jeanne Singh , Karthik Vaideeswaran
Inventor： John Krawczyk , James Mrvos , Girish Patil , Jason Vanderpool , Brian Hart , Christopher Money , Jeanne Singh , Karthik Vaideeswaran
IPC: G03C5/00 , H01L21/461 , H01L21/302
CPC classification number: B41J2/1603 , B41J2/1628 , B41J2/1631 , B41J2/1645 , B81B2201/052 , B81C1/00531
Abstract: A method of etching a semiconductor substrate. The method includes the steps of applying a photoresist etch mask layer to a device surface of the substrate. A select first area of the photoresist etch mask is masked, imaged and developed. A select second area of the photoresist etch mask layer is irradiated to assist in post etch stripping of the etch mask layer from the select second area. The substrate is etched to form fluid supply slots through a thickness of the substrate. At least the select second area of the etch mask layer is removed from the substrate, whereby mask layer residue formed from the select second area of the etch mask layer is significantly reduced.
Abstract translation: 蚀刻半导体衬底的方法。 该方法包括以下步骤：将光致抗蚀剂蚀刻掩模层施加到衬底的器件表面。 光刻胶蚀刻掩模的选择第一区被掩蔽，成像和显影。 照射光致抗蚀剂蚀刻掩模层的选择的第二区域以辅助蚀刻掩模层从选择的第二区域的后蚀刻剥离。 蚀刻基板以形成通过基板的厚度的流体供给槽。 至少蚀刻掩模层的选择第二区域从衬底去除，由此从蚀刻掩模层的选择的第二区域形成的掩模层残留物显着减少。
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公开(公告)号：US07271105B2
公开(公告)日：2007-09-18
申请号：US10941404
申请日：2004-09-15
Applicant: John W. Krawczyk , James M. Mrvos , Girish S. Patil , Jason T. Vanderpool , Brian C. Hart , Christopher J. Money , Jeanne M. Saldanha Singh , Karthik Vaideeswaran
Inventor： John W. Krawczyk , James M. Mrvos , Girish S. Patil , Jason T. Vanderpool , Brian C. Hart , Christopher J. Money , Jeanne M. Saldanha Singh , Karthik Vaideeswaran
IPC: H01L21/461
CPC classification number: B41J2/1603 , B41J2/1628 , B41J2/1631 , B41J2/1645 , B81B2201/052 , B81C1/00531
Abstract: A method of etching a semiconductor substrate. The method includes the steps of applying a photoresist etch mask layer to a device surface of the substrate. A select first area of the photoresist etch mask is masked, imaged and developed. A select second area of the photoresist etch mask layer is irradiated to assist in post etch stripping of the etch mask layer from the select second area. The substrate is etched to form fluid supply slots through a thickness of the substrate. At least the select second area of the etch mask layer is removed from the substrate, whereby mask layer residue formed from the select second area of the etch mask layer is significantly reduced.
Abstract translation: 蚀刻半导体衬底的方法。 该方法包括以下步骤：将光致抗蚀剂蚀刻掩模层施加到衬底的器件表面。 光刻胶蚀刻掩模的选择第一区被掩蔽，成像和显影。 照射光致抗蚀剂蚀刻掩模层的选择的第二区域以辅助蚀刻掩模层从选择的第二区域的后蚀刻剥离。 蚀刻基板以形成通过基板的厚度的流体供给槽。 至少蚀刻掩模层的选择第二区域从衬底去除，由此从蚀刻掩模层的选择的第二区域形成的掩模层残留物显着减少。
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公开(公告)号：US06881677B1
公开(公告)日：2005-04-19
申请号：US10803009
申请日：2004-03-17
Applicant: Girish Shivaji Patil , Karthik Vaideeswaran
Inventor： Girish Shivaji Patil , Karthik Vaideeswaran
IPC: B41J2/16 , H01L21/302 , H01L21/461
CPC classification number: B81C1/00531 , B41J2/1603 , B41J2/1628 , B41J2/1631 , B81B2201/052
Abstract: A method for forming a fluid feed via in a semiconductor substrate chip for a micro-fluid ejection head. The method includes applying a photoresist planarization and protection layer to a first surface of the chip. The photoresist planarization and protection layer is patterned and developed to define at least one fluid feed via location. A strippable layer is applied to the photoresist planarization and protection layer on the chip. The strippable layer is patterned and developed with a photomask to define the at least one fluid feed via location in the strippable layer. The chip is then dry etched to form at least one fluid feed via in the defined feed via location. Before or after etching the chip, deprotection of the strippable layer is induced so that the strippable layer can be substantially removed with a solvent without substantially affecting the photoresist planarization and protection layer.
Abstract translation: 一种用于在用于微流体喷射头的半导体衬底芯片中形成流体供给通孔的方法。 该方法包括将光致抗蚀剂平坦化和保护层应用于芯片的第一表面。 光致抗蚀剂平坦化和保护层被图案化和显影以限定至少一个通过位置的流体馈送。 可剥离层被施加到芯片上的光致抗蚀剂平坦化和保护层。 可剥离层被图案化并用光掩模显影以限定通过可剥离层中的位置的至少一个流体进料。 然后将芯片干蚀刻以在定义的进料通过位置形成至少一个流体进料通孔。 在蚀刻芯片之前或之后，诱导可剥离层的脱保护，使得可剥离层可以基本上用溶剂除去而基本上不影响光致抗蚀剂平坦化和保护层。
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公开(公告)号：US20110079962A1
公开(公告)日：2011-04-07
申请号：US12897398
申请日：2010-10-04
Applicant: Donald M. Munro , Jon M. Lenhert , Karthik Vaideeswaran , Jose R. Sousa
Inventor： Donald M. Munro , Jon M. Lenhert , Karthik Vaideeswaran , Jose R. Sousa
CPC classification number: F16J15/3212 , F16J15/3236
Abstract: A seal includes a seal body including an annular cavity, and an annular spring within the annular cavity. The seal body, the seal body includes a composite material having a thermoplastic material and a filler. The composite material can have a Young's Modulus of at least about 0.5 GPa, a volume resistitivity of not greater than about 200 Ohm-cm, an elongation of at least about 20%, a surface resistitivity of not greater than about 104 Ohm/sq, or any combination thereof.
Abstract translation: 密封件包括包括环形空腔的密封体和环形空腔内的环形弹簧。 密封体，密封体包括具有热塑性材料和填料的复合材料。 复合材料可以具有至少约0.5GPa的杨氏模量，不大于约200欧姆 - 厘米的体积电阻率，至少约20％的伸长率，不大于约104欧姆/平方厘米的表面电阻率， 或其任何组合。
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Patent Agency Ranking
公开(公告)号：US20100224400A1
公开(公告)日：2010-09-09
申请号：US12719377
申请日：2010-03-08
Applicant: Jon M. Lenhert , Karthik Vaideeswaran , Donald M. Munro
Inventor： Jon M. Lenhert , Karthik Vaideeswaran , Donald M. Munro
Abstract: A cross-diametric compression spring includes a conductive ribbon formed into an overlapping helical coil wherein adjacent loops of the conductive ribbon overlap. The conductive ribbon has a width extending substantially parallel to length of the overlapping helical coil.
Abstract translation: 交叉直径压缩弹簧包括形成为重叠螺旋线圈的导电带，其中导电带的相邻环重叠。 导电带具有基本上平行于重叠的螺旋线圈的长度延伸的宽度。
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公开(公告)号：US20100116422A1
公开(公告)日：2010-05-13
申请号：US12614191
申请日：2009-11-06
Applicant: Karthik Vaideeswaran , Jose R. Sousa , Hamid Reza Ghalambor , Sarah L. Clark , Ceyhan Celik , Gary Charles Hildreth, JR. , Helina Joshi
Inventor： Karthik Vaideeswaran , Jose R. Sousa , Hamid Reza Ghalambor , Sarah L. Clark , Ceyhan Celik , Gary Charles Hildreth, JR. , Helina Joshi
IPC: B29C53/36
CPC classification number: B29C66/1142 , B29C53/083 , B29C53/36 , B29C65/1425 , B29C65/1432 , B29C65/16 , B29C65/18 , B29C65/20 , B29C65/2076 , B29C66/0242 , B29C66/034 , B29C66/5261 , B29C66/5268 , B29C66/71 , B29C66/73117 , B29C66/7315 , B29C66/73151 , B29C66/73921 , B29C66/91411 , B29C66/91445 , B29C66/919 , B29C66/91935 , B29C66/91943 , B29C66/91945 , B29C71/02 , B29C2071/022 , B29D99/0085 , B29K2995/007 , B29K2995/0089 , B29L2031/265 , B29L2031/709 , B29L2031/7096 , C09K3/10 , C09K2200/0657 , Y10T156/1036 , B29K2427/18 , B29K2071/00 , B29K2023/0683 , B29K2027/12 , B29K2077/00 , B29K2079/00 , B29K2079/085 , B29K2081/04 , B29K2081/06
Abstract: A method of forming a seal ring includes heating an extruded rod to a temperature above a glass transition temperature. The extruded rod has first and second ends. The method further includes bending the extruded rod into a circular structure while the temperature is above the glass transition temperature, joining the first and second ends of the extruded rod to form a semi-finished ring, and annealing the semi-finished ring.
Abstract translation: 形成密封环的方法包括将挤出的棒加热到高于玻璃化转变温度的温度。 挤压棒具有第一和第二端。 该方法还包括在温度高于玻璃化转变温度时将挤出的棒弯曲成圆形结构，将挤压棒的第一和第二端接合以形成半成品环，并对半成品环进行退火。
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公开(公告)号：US07041226B2
公开(公告)日：2006-05-09
申请号：US10701225
申请日：2003-11-04
Applicant: Karthik Vaideeswaran , Andrew L. McNees , John W. Krawczyk , James M. Mrvos , Cory N. Hammond , Mark L. Doerre , Jason T. Vanderpool , Girish S. Patil , Christopher J. Money , Gary R. Williams , Richard L. Warner
Inventor： Karthik Vaideeswaran , Andrew L. McNees , John W. Krawczyk , James M. Mrvos , Cory N. Hammond , Mark L. Doerre , Jason T. Vanderpool , Girish S. Patil , Christopher J. Money , Gary R. Williams , Richard L. Warner
CPC classification number: B41J2/1632 , B41J2/14145 , B41J2/1603 , B41J2/1623 , B41J2/1628 , B41J2/1631 , B41J2/1645 , B41J2/1646
Abstract: A method for improving fluidic flow for a microfluidic device having a through hole or slot therein. The method includes the steps of forming one or more openings through at least part of a thickness of a substrate from a first surface to an opposite second surface using a reactive ion etching process whereby an etch stop layer is applied to side wall surfaces in the one or more openings during alternating etching and passivating steps as the openings are etched through at least a portion of the substrate. Substantially all of the etch stop layer coating is removed from the side wall surfaces by treating the side wall surfaces using a method selected from chemical treatment and mechanical treatment, whereby a surface energy of the treated side wall surfaces is increased relative to a surface energy of the side wall surfaces containing the etch stop layer coating.
Abstract translation: 一种用于改善其中具有通孔或槽的微流体装置的流体流动的方法。 该方法包括以下步骤：使用反应离子蚀刻工艺从基板的第一表面至相对的第二表面形成穿过衬底的至少一部分厚度的一个或多个开口，由此将蚀刻停止层施加到一个侧壁表面 或者在交替蚀刻和钝化步骤期间，当开口被蚀刻通过衬底的至少一部分时，可以有更多的开口。 通过使用选自化学处理和机械处理的方法处理侧壁表面，从侧壁表面去除基本上所有的蚀刻停止层涂层，由此所处理的侧壁表面的表面能相对于 所述侧壁表面包含所述蚀刻停止层涂层。
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公开(公告)号：US20110156361A1
公开(公告)日：2011-06-30
申请号：US12981295
申请日：2010-12-29
Applicant: Hamid Reza Ghalambor , Karthik Vaideeswaran
Inventor： Hamid Reza Ghalambor , Karthik Vaideeswaran
CPC classification number: F16J15/3452 , B23K26/0093 , F16F1/02 , F16J15/3212 , F16J15/3236 , Y10T29/49609
Abstract: A seal includes a polymeric jacket defining a seal surface and an inner cavity extending within the polymeric jacket along a length of the polymeric jacket. The seal further includes a spring extending within the inner cavity and including a plurality of laser cut spring elements. The seal can be disposed between a static component and a rotatable component.
Abstract translation: 密封件包括限定密封表面的聚合物护套和沿着聚合物护套的长度在聚合护套内延伸的内腔。 密封件还包括在内腔内延伸并包括多个激光切割弹簧元件的弹簧。 密封件可以设置在静态部件和可旋转部件之间。
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公开(公告)号：US07938975B2
公开(公告)日：2011-05-10
申请号：US11780234
申请日：2007-07-19
Applicant: John W. Krawczyk , James M. Mrvos , Girish S. Patil , Jason T. Vanderpool , Brian C. Hart , Christopher J. Money , Jeanne M. Saldanha Singh , Karthik Vaideeswaran
Inventor： John W. Krawczyk , James M. Mrvos , Girish S. Patil , Jason T. Vanderpool , Brian C. Hart , Christopher J. Money , Jeanne M. Saldanha Singh , Karthik Vaideeswaran
IPC: G11B5/127
CPC classification number: B41J2/1603 , B41J2/1628 , B41J2/1631 , B41J2/1645 , B81B2201/052 , B81C1/00531
Abstract: A method of etching a semiconductor substrate. The method includes the steps of applying a photoresist etch mask layer to a device surface of the substrate. A select first area of the photoresist etch mask is masked, imaged and developed. A select second area of the photoresist etch mask layer is irradiated to assist in post etch stripping of the etch mask layer from the select second area. The substrate is etched to form fluid supply slots through a thickness of the substrate. At least the select second area of the etch mask layer is removed from the substrate, whereby mask layer residue formed from the select second area of the etch mask layer is significantly reduced.
Abstract translation: 蚀刻半导体衬底的方法。 该方法包括以下步骤：将光致抗蚀剂蚀刻掩模层施加到衬底的器件表面。 光刻胶蚀刻掩模的选择第一区被掩蔽，成像和显影。 照射光致抗蚀剂蚀刻掩模层的选择的第二区域以辅助蚀刻掩模层从选择的第二区域的后蚀刻剥离。 蚀刻基板以形成通过基板的厚度的流体供给槽。 至少蚀刻掩模层的选择第二区域从衬底去除，由此从蚀刻掩模层的选择的第二区域形成的掩模层残留物显着减少。
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