Abstract:
The medication administration accuracy of a number of hospitals is compared and reports are produced. Data is received from each of the reporting hospitals including dosage error information and matching characteristics on which the hospitals can be compared. The received data is merged to provide a medication accuracy comparison database, and comparison groups are established based on a predetermined characteristic of each hospital. An accuracy rate is calculated for each hospital, and a report is produced comparing the medication administration accuracy of each reporting hospital with other hospitals in the associated comparison group.
Abstract:
An educational device, such as a flipbook, is designed and utilized with an instructional methodology for teaching students about the structure of written words. The orthographic patterns found in English single-syllable words and syllables are shown using color-coded sets of pages, each imprinted with a letter or letter cluster comprising vowels, r—controlled vowels, vowel teams, initial and final consonants and consonant digraphs, initial and final consonant blends, or either of two silent es—“marvelous e” and “not so marvelous e.” Sets of prefix and suffix pages are also used, along with a schwa page, to indicate the sound of an unaccented vowel. Like letters, or letter clusters, can be substituted for each other in flipbook fashion, consonants for consonants and vowels for vowels, so that by rotating various flipbook pages, hat can be changed to hot, or hop, or chop.
Abstract:
The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port snning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
Abstract:
A system and method of reducing the input and output pins used to interface a fast serial port Ethernet processing system using multiplexing. Using the system of the present invention, four pins can allow a plurality of Ethernet communication paths to be connected to a single processor on a substrate. These four connections include a clocking input as well as a strobe signal which coordinates the multiplexing and identifies the time period for a predetermined source. The physical layer and the processor are each provided with a multiplexor which is controlled by the strobe to select the network to be coupled at any given time. The multiplexor includes a counter which is incremented by the clocking input and reset by the strobe signal.
Abstract:
In a first aspect, a first method is provided for controlling the flow of data between a first and second clock domain. The first method includes the steps of (1) selecting one of a plurality of ports included in a physical layer interface in the second clock domain to which to send data; and (2) transmitting data from a transmit buffer in the first clock domain to the selected port in the physical layer interface in the second clock domain. Numerous other aspects are provided.
Abstract:
In a first aspect, a first method is provided for controlling the flow of data between a first and second clock domain. The first method includes the steps of (1) selecting one of a plurality of ports included in a physical layer interface in the second clock domain to which to send data; and (2) transmitting data from a transmit buffer in the first clock domain to the selected port in the physical layer interface in the second clock domain. Numerous other aspects are provided.
Abstract:
A test pattern is loaded into a driver data shift register and sent from a driver chip to a receive chip over an M bit bus (0 to M−1). The test pattern is also generated at the receiver chip and used to compare to the actual received data. Failed compares are stored as logic ones in a bit error register (BER). A counter determines the number of failures by counting logic ones from the BER. The contents of a error position counter are latched in a error position latch and used to load a logic one (at the error bit position) into daisy chained self-heal control registers (SCR) in the receiver chip and the driver chip. The SCR sets a logic one into all bit positions after the error bit isolating the failed bit path and adding a spare bit path which is in bit position M.