公开(公告)号：US06566183B1

公开(公告)日：2003-05-20

申请号：US10017192

申请日：2001-12-12

Applicant: Steven A. Chen ,  Lee Luo ,  Kegang Huang ,  Tzy-Tzan Fu ,  Kuan-Ting Lin ,  Hung-Chuan Chen

Inventor： Steven A. Chen ,  Lee Luo ,  Kegang Huang ,  Tzy-Tzan Fu ,  Kuan-Ting Lin ,  Hung-Chuan Chen

IPC: H01L218238

CPC classification number: H01L29/6659 ,  H01L21/3185 ,  H01L29/6656 ,  H01L29/7833

Abstract: The invention provides a method of making a transistor. A gate dielectric layer is formed on a semiconductor substrate. A gate is formed on the dielectric layer, the gate having an exposed upper surface and exposed side surfaces. A first silicon nitride layer having a first thickness is deposited over the gate, for example over an oxide layer on the gate, at a first deposition rate. A second silicon nitride layer having a second thickness is deposited over the first silicon nitride layer at a second deposition rate, the second thickness being more that the first thickness and the second deposition rate being more than the first deposition rate. The first silicon nitrogen layer then has a lower hydrogen concentration. At least the second silicon nitride layer (or a silicon oxide layer in the case of an ONO spacer) is etched to leave spacers next to the side surfaces while exposing the upper surface of the gate and areas of the substrate outside the spacers.

Abstract translation: 本发明提供一种制造晶体管的方法。 在半导体衬底上形成栅介电层。 栅极形成在电介质层上，栅极具有暴露的上表面和暴露的侧表面。 具有第一厚度的第一氮化硅层以第一沉积速率沉积在栅极上，例如在栅极上的氧化物层上方。 具有第二厚度的第二氮化硅层以第二沉积速率沉积在第一氮化硅层上，第二厚度大于第一厚度和第二沉积速率大于第一沉积速率。 然后第一硅氮层具有较低的氢浓度。 蚀刻至少第二氮化硅层（或在ONO间隔物的情况下的氧化硅层），以使隔板靠近侧表面，同时将栅极的上表面和衬底的区域暴露在间隔物外部。

公开(公告)号：US10239183B2

公开(公告)日：2019-03-26

申请号：US15422125

申请日：2017-02-01

Applicant: Chien-Hung Sung ,  Kuan-Ting Lin

Inventor： Chien-Hung Sung ,  Kuan-Ting Lin

IPC: B24B37/26 ,  B24D18/00 ,  B24B37/22

Abstract: A chemical mechanical polishing pad includes a base portion and a polishing portion. The base portion has opposite first and second side surfaces. The polishing portion extends from the first side surface away from the second side surface, has a polishing surface facing away from the base portion, and has at least one trench formed in the polishing surface. Each of the trenches has an opening defined by the polishing surface. A horizontal width of the opening of each of the trenches is equal to or smaller than that of the remaining portion of the trench. The chemical mechanical polishing pad is made by laminating a plurality of polymer layers.

公开(公告)号：US20110148526A1

公开(公告)日：2011-06-23

申请号：US12803578

申请日：2010-06-30

Applicant: Shey-Shi Lu ,  Yu-Hsiang Wang ,  Kuan-Ting Lin

Inventor： Shey-Shi Lu ,  Yu-Hsiang Wang ,  Kuan-Ting Lin

IPC: H03F3/16

CPC classification number: H03F1/223 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/456 ,  H03F2200/492 ,  H03F2203/7236

Abstract: The present invention relates a low noise amplifier with adaptive frequency responses and method of altering frequency responses thereof. The low noise amplifier comprises an inductive degeneration circuit, N cascode circuits and N switches. The inductive degeneration circuit has an input impedance and a frequency response characteristic. Each of the cascode circuits is connected in parallel to the inductive degeneration circuit. Each of the switches is connected to a corresponding cascode circuit respectively. Each of the cascode circuit is turned ON or OFF by enabling or disabling the corresponding switches to alter the frequency response characteristic.

Abstract translation: 本发明涉及具有自适应频率响应的低噪声放大器和改变其频率响应的方法。 低噪声放大器包括电感退化电路，N个共源共栅电路和N个开关。 感应退化电路具有输入阻抗和频率响应特性。 每个共源共栅电路与电感性退化电路并联连接。 每个开关分别连接到相应的共源共栅电路。 通过启用或禁用相应的开关来改变频率响应特性，每个共源共享电路被接通或关断。

公开(公告)号：US20110068283A1

公开(公告)日：2011-03-24

申请号：US12695557

申请日：2010-01-28

Applicant: Shey-Shi Lu ,  Ying-Jay Yang ,  Shuo-Hung Chang ,  Jian-Yu Hsieh ,  Kuan-Ting Lin ,  Tao Wang ,  Chih-Chung Su ,  Cheng-Hung Li ,  Neng-Kai Chang

Inventor： Shey-Shi Lu ,  Ying-Jay Yang ,  Shuo-Hung Chang ,  Jian-Yu Hsieh ,  Kuan-Ting Lin ,  Tao Wang ,  Chih-Chung Su ,  Cheng-Hung Li ,  Neng-Kai Chang

IPC: G21F1/10

CPC classification number: H05K9/0088

Abstract: The invention provides electromagnetic wave absorption components and device. The electromagnetic wave absorption component includes an electromagnetic shield constituted by at least one material selected from the group consisting of a carbon nanocoil and a carbon fiber, and a solidified layer formed of a mixture of a solidifiable material and the electromagnetic shield after solidification. Another embodiment of the electromagnetic wave absorption component includes an electromagnetic shield constituted by at least one material selected from the group consisting of a carbon nanocoil and a carbon fiber, and a solidified layer, formed by solidifying a solidifiable material, applicable to encapsulating the electromagnetic shield. Further, the electromagnetic wave absorption device is formed by stacking at least two of the above-mentioned electromagnetic wave absorption components.

Abstract translation: 本发明提供电磁波吸收组件和装置。 电磁波吸收部件包括由选自碳纳米线和碳纤维的至少一种材料构成的电磁屏蔽，以及在固化后由可固化材料和电磁屏蔽的混合物形成的固化层。 电磁波吸收部件的另一实施例包括由选自碳纳米线和碳纤维的至少一种材料构成的电磁屏蔽，以及通过固化可固化材料形成的固化层，其可用于封装电磁屏蔽 。 此外，电磁波吸收装置通过堆叠至少两个上述电磁波吸收组件而形成。

公开(公告)号：US20180043499A1

公开(公告)日：2018-02-15

申请号：US15422125

申请日：2017-02-01

Applicant: Chien-Hung SUNG ,  Kuan-Ting LIN

Inventor： Chien-Hung SUNG ,  Kuan-Ting LIN

IPC: B24B37/26 ,  B24D18/00

CPC classification number: B24B37/26 ,  B24B37/22 ,  B24D18/00

Abstract: A chemical mechanical polishing pad includes a base portion and a polishing portion. The base portion has opposite first and second side surfaces. The polishing portion extends from the first side surface away from the second side surface, has a polishing surface facing away from the base portion, and has at least one trench formed in the polishing surface. Each of the trenches has an opening defined by the polishing surface. A horizontal width of the opening of each of the trenches is equal to or smaller than that of the remaining portion of the trench. The chemical mechanical polishing pad is made by laminating a plurality of polymer layers.

公开(公告)号：US06596576B2

公开(公告)日：2003-07-22

申请号：US10032359

申请日：2001-12-21

Applicant: Tzy-Tzan Fu ,  Kuan-Ting Lin ,  Chao-Sheng Chou

Inventor： Tzy-Tzan Fu ,  Kuan-Ting Lin ,  Chao-Sheng Chou

IPC: H01L218238

CPC classification number: H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor device having a gate structure comprising SiO2 and Si3N4 that exhibits reduced hydrogen diffusion during low temperature chemical vapor deposition of silicon nitride. In the method, a silicon dioxide (SiO2) layer is deposited on a wafer after a gate structure is fabricated. A barrier layer is formed on the silicon dioxide (SiO2) layer. Then a silicon nitride layer is formed over it by low temperature chemical vapor deposition. The barrier layer reduces, and may even altogether prevent, diffusion of the hydrogen absorbed by the silicon nitride layer into the gate oxide and channel during the low temperature chemical vapor deposition of silicon nitride.

Abstract translation: 一种制造半导体器件的方法，该半导体器件具有包含SiO 2和Si 3 N 4的栅结构，其在氮化硅的低温化学气相沉积期间显示出减少的氢扩散。 在该方法中，在制造栅极结构之后，在晶片上沉积二氧化硅（SiO 2）层。 在二氧化硅（SiO 2）层上形成阻挡层。 然后通过低温化学气相沉积在其上形成氮化硅层。 在氮化硅的低温化学气相沉积期间，阻挡层减少并甚至可以防止由氮化硅层吸收的氢扩散到栅极氧化物和沟道中。