公开(公告)号：US08674485B1

公开(公告)日：2014-03-18

申请号：US12963431

申请日：2010-12-08

Applicant: Gi Jeong Kim ,  Jae Yoon Kim ,  Kyu Won Lee

Inventor： Gi Jeong Kim ,  Jae Yoon Kim ,  Kyu Won Lee

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49558 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: In one embodiment, a semiconductor package includes a generally planar die paddle or die pad that defines multiple peripheral edge segments, and includes one or more tie bars protruding therefrom. In addition, the semiconductor package includes a plurality of leads, portions of which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body. The one or more tie bars and the plurality of leads include downsets that are sized and oriented relative to each other to facilitate enhanced manufacturing.

Abstract translation: 在一个实施例中，半导体封装包括限定多个周边边缘段的大致平面的管芯焊盘或管芯焊盘，并且包括从其突出的一个或多个连接杆。 此外，半导体封装包括多个引线，其多个引线从半导体封装的封装主体的相应侧表面突出。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到至少一些引线。 芯片焊盘，引线和半导体管芯的至少一部分被封装体封装。 一个或多个连接杆和多个引线包括相对于彼此定尺寸和定向的下沉，以有助于增强制造。

公开(公告)号：US20130249076A1

公开(公告)日：2013-09-26

申请号：US13424710

申请日：2012-03-20

Applicant: Soo Won Lee ,  Kyu Won Lee ,  Eun Jin Jeong

Inventor： Soo Won Lee ,  Kyu Won Lee ,  Eun Jin Jeong

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L24/13 ,  H01L21/4846 ,  H01L23/498 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05181 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/16112 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01007 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01023 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the first conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad.

Abstract translation: 半导体器件具有基板。 第一导电层形成在衬底上。 引线板上的双面电镀凸块形成在衬底上。 在第一导电层和基板之上形成绝缘层。 使用激光直接烧蚀工艺去除铅焊盘上的双面电镀凸块上绝缘层的一部分。 绝缘层是层叠层。 导线焊盘上的双面电镀凸块在导线焊盘上有一个很大的凹凸。 半导体管芯安装在衬底上。 半导体管芯具有复合导电互连结构。 半导体管芯具有第一凸块和在第一凸块和第二凸块之间具有从90-150微米的间距的第二凸块。 双面电镀接触焊盘形成在与双面电镀凸块焊盘相对的基板的表面上。

公开(公告)号：US08461696B2

公开(公告)日：2013-06-11

申请号：US12647953

申请日：2009-12-28

Applicant: Kyu Won Lee ,  Qwan Ho Chung

Inventor： Kyu Won Lee ,  Qwan Ho Chung

IPC: H01L23/12 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L24/27 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/3512

Abstract: A substrate for a semiconductor package is provided having first and second core layers defining a cavity having an adhesive member and sized and shaped to receive a semiconductor chip. The semiconductor package further having a connection member formed on a bond finger and connected to a via pattern formed through the first and second core layers. A stack package is also provided having multiple substrates.

Abstract translation: 提供了一种用于半导体封装的衬底，其具有限定具有粘合构件的空腔的第一和第二芯层，并且其尺寸和形状用于容纳半导体芯片。 所述半导体封装还具有连接构件，所述连接构件形成在接合指状物上并且连接到通过所述第一和第二芯层形成的通孔图案。 还提供具有多个基板的堆叠封装。

公开(公告)号：US08334590B1

公开(公告)日：2012-12-18

申请号：US12204692

申请日：2008-09-04

Applicant: Yoon Ha Jung ,  Kyu Won Lee ,  Chan Yok Park

Inventor： Yoon Ha Jung ,  Kyu Won Lee ,  Chan Yok Park

IPC: H01L23/04

CPC classification number: H01L21/568 ,  H01L23/3135 ,  H01L2924/0002 ,  H05K1/186 ,  H05K3/4652 ,  H01L2924/00

Abstract: A semiconductor device for use in a printed circuit board is provided. In the semiconductor device, metal pillars are disposed perpendicular to bond pads of a semiconductor die. This configuration eliminates the need to form via holes for the connection of interconnection layers and the bond pads of the semiconductor die, thus simplifying the fabrication procedure of the semiconductor device. In addition, the semiconductor die is embedded in the semiconductor device. Based on this configuration, the use of the semiconductor device in a printed circuit board facilitates the stacking of a plurality of semiconductor dies and can reduce the thickness required for the stack, which make the semiconductor device light in weight and small in thickness and size.

Abstract translation: 提供了一种用于印刷电路板的半导体器件。 在半导体器件中，金属柱垂直于半导体管芯的焊盘设置。 这种配置消除了形成用于连接互连层和半导体管芯的接合焊盘的通孔的需要，从而简化了半导体器件的制造过程。 此外，半导体管芯被嵌入在半导体器件中。 基于这种配置，在印刷电路板中使用半导体器件有助于多个半导体管芯的堆叠，并且可以减小堆叠所需的厚度，这使得半导体器件重量轻，厚度和尺寸小。

公开(公告)号：US08298155B2

公开(公告)日：2012-10-30

申请号：US12441353

申请日：2007-07-27

Applicant: Dong Hoon Lee ,  Jin Dong Kim ,  Yun Sung Ro ,  Jung Hwan Ok ,  Kyu Won Lee

Inventor： Dong Hoon Lee ,  Jin Dong Kim ,  Yun Sung Ro ,  Jung Hwan Ok ,  Kyu Won Lee

IPC: A61B5/00 ,  H04R29/00

CPC classification number: A61B5/121

Abstract: The present invention relates to a pure tone audiometer, and more particularly, to a pure tone audiometer with automated masking which is capable of automatically performing air-conduction and bone-conduction hearing tests and automatically performing a masking test, if necessary, so that a person obtains an accurate pure tone hearing threshold without others' assistance. The pure tone audiometer of the present invention can accurately perform the pure tone hearing test with automated masking without assistance from a doctor or an audiologist. Thus, with the pure tone audiometer, people can easily check their hearing ability for prevention and early detection of hearing loss and take swift action to cure hearing loss.

Abstract translation: 本发明涉及一种纯音听力计，更具体地说，涉及一种具有自动掩蔽功能的纯音听力计，它能够自动进行空气传导和骨传导听力测试，并在必要时自动执行掩蔽测试，使得 没有其他人的帮助，人们获得准确的纯音听阈。 本发明的纯音听力计可以在没有医生或听力学家的帮助的情况下自动掩蔽地进行纯音听觉测试。 因此，使用纯音听力计，人们可以轻松检查听力的预防和早期发现听力损失，并采取迅速措施治愈听力损失。

公开(公告)号：US08093050B2

公开(公告)日：2012-01-10

申请号：US12671362

申请日：2007-08-17

Applicant: Yee Sook Cho ,  Kyu-Won Lee

Inventor： Yee Sook Cho ,  Kyu-Won Lee

IPC: C12N15/00

CPC classification number: A61K31/436 ,  C12N5/0654 ,  C12N2500/38 ,  C12N2500/42 ,  C12N2501/04 ,  C12N2501/39 ,  C12N2501/70 ,  C12N2502/02

Abstract: Disclosed are a composition for introducing the osteogenic differentiation of human embryonic stem cells and a method for differentiating human embryonic stem cells into an osteoblastic lineage by inhibiting the mTOR signaling pathway. When cultured in the presence of an inhibitor of the mTOR signaling pathway, human embryonic stem cells are effectively induced to differentiate into an osteoblastic lineage. The osteogenic differentiation of human embryonic stem cells using the method and the composition is useful in examining the development and differentiation mechanism of osteoblasts and the cause of metabolic bone diseases, including osteoporosis. In addition, the method and the composition can be applied to the development of osteogenic differentiation techniques for generating clinically useful, terminally differentiated mature cells or progenitor cells.

Abstract translation: 公开了用于引入人胚胎干细胞的成骨分化的组合物和通过抑制mTOR信号通路将人胚胎干细胞分化成成骨细胞谱系的方法。 当在mTOR信号通路抑制剂存在下培养时，人胚胎干细胞被有效诱导分化为成骨细胞谱系。 使用该方法和组合物的人胚胎干细胞的成骨分化可用于检查成骨细胞的发育和分化机制以及代谢骨疾病（包括骨质疏松症）的原因。 此外，该方法和组合物可用于开发用于产生临床有用的终末分化的成熟细胞或祖细胞的成骨分化技术。

公开(公告)号：US20110189928A1

公开(公告)日：2011-08-04

申请号：US13050325

申请日：2011-03-17

Applicant: Hee Min SHIN ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Kyu Won LEE

Inventor： Hee Min SHIN ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Kyu Won LEE

IPC: B24B1/00 ,  B32B3/14 ,  C09J7/02

CPC classification number: H01L21/6835 ,  C09J7/20 ,  C09J2201/28 ,  C09J2203/326 ,  H01L21/67005 ,  H01L21/67132 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  Y10T156/10 ,  Y10T156/17 ,  Y10T428/215

Abstract: A wafer mount tape, a wafer processing apparatus and an associated method of using the wafer mount tape for use in wafer thinning operations is presented. The wafer mount tape includes a tape body, a first adhesive member and a second adhesive member. The tape body has a first region, a second region and a third region. The first region of the tape body is for being disposed onto a wafer. The second region of the tape body is defined along a periphery of the first region. The third region of the tape body is defined along a periphery of the second region. The first adhesive is member is disposed at the first region. The second adhesive member is disposed at the third region.

Abstract translation: 提出了一种晶片安装带，晶片处理设备和使用晶片安装带用于晶片间隔操作的相关方法。 晶片安装带包括带体，第一粘合构件和第二粘合构件。 带体具有第一区域，第二区域和第三区域。 带体的第一区域用于设置在晶片上。 带体的第二区域沿着第一区域的周边限定。 带体的第三区域沿着第二区域的周边限定。 第一粘合剂是构件设置在第一区域。 第二粘合构件设置在第三区域。

公开(公告)号：US20090064731A1

公开(公告)日：2009-03-12

申请号：US12230630

申请日：2008-09-02

Applicant: Kyu-Won Lee

Inventor： Kyu-Won Lee

IPC: D06F37/02 ,  B08B3/00

CPC classification number: D06F39/008

Abstract: Disclosed are the steam generator and the washing/drying machine having the same, the steam generator including: a case having an opening at one side thereof, a heating unit formed to penetrate the opening, and a fixing assembly mounted at the opening so as to seal the opening and supporting the heating unit, wherein the fixing assembly includes a sealing member for sealing the opening, and the opening includes a leakage prevention portion for preventing a gap formation between the opening and the sealing member when the sealing member is deformed, thereby preventing a leakage between the opening of the case and the sealing member even though the case or the sealing member is thermally deformed.

Abstract translation: 蒸汽发生器和具有该蒸汽发生器的洗涤/干燥机具有以下特征：蒸汽发生器包括：在一侧具有开口的壳体，形成为穿透开口的加热单元，以及安装在开口处的固定组件， 密封开口并支撑加热单元，其中固定组件包括用于密封开口的密封构件，并且开口包括防漏部分，用于防止当密封构件变形时开口和密封构件之间的间隙形成，从而 即使壳体或密封构件发生热变形，防止了壳体的开口和密封构件之间的泄漏。

公开(公告)号：US20080006063A1

公开(公告)日：2008-01-10

申请号：US11819320

申请日：2007-06-26

Applicant: In Geun Ahn ,  Kyu Won Lee ,  Seong Moon

Inventor： In Geun Ahn ,  Kyu Won Lee ,  Seong Moon

IPC: D06F39/04 ,  F22B1/30

CPC classification number: F22B1/284 ,  D06F39/008

Abstract: A steam generating device and a washing machine having the same are disclosed. The steam generating device includes a lower housing including a main portion for receiving a heater, and connecting portions extending outwardly from the main portion, the lower housing defining a water chamber for containing water, an upper housing connected to the connecting portions, the upper housing defining a steam chamber for containing steam, a water level sensor for sensing a level of water contained in the water chamber, and a receptacle for protecting the water level sensor. The receptacle has an opening for allowing water to be introduced into the receptacle, and is substantially aligned with an inner surface of the lower housing or is arranged at a position spaced apart from the heater by a longer distance than the inner surface of the lower housing.

Abstract translation: 公开了一种蒸汽发生装置和具有该蒸汽发生装置的洗衣机。 蒸汽发生装置包括：下壳体，其包括用于接收加热器的主体部分和从主要部分向外延伸的连接部分，下壳体限定用于容纳水的水室，连接到连接部分的上壳体， 限定用于容纳蒸汽的蒸汽室，用于感测水室中容纳的水位的水位传感器和用于保护水位传感器的容器。 容器具有用于允许水引入到容器中的开口，并且基本上与下壳体的内表面对准或者布置在与加热器间隔开比距下壳体的内表面更长的距离 。

公开(公告)号：US20120018879A1

公开(公告)日：2012-01-26

申请号：US12981386

申请日：2010-12-29

Applicant: Hee-Min SHIN ,  Cheol-Ho JOH ,  Eun-Hye DO ,  Ji-Eun KIM ,  Kyu-Won LEE

Inventor： Hee-Min SHIN ,  Cheol-Ho JOH ,  Eun-Hye DO ,  Ji-Eun KIM ,  Kyu-Won LEE

IPC: H01L25/11 ,  H01L21/98

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/117 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Abstract translation: 叠层封装包括覆盖膜，具有附接到覆盖膜的第一半导体芯片的第一封装，形成为密封第一半导体芯片的第一粘合构件和覆盖膜的表面，以及第一电路图案 其设置在第一粘合构件上并与第一半导体芯片电连接; 第二封装，设置在所述第一封装上，具有与所述第一电路图案电连接的第二半导体芯片，形成为密封所述第二半导体芯片的第二粘合构件，以及形成在所述第二粘合剂上的第二电路图案 以及形成为穿过第二电路图案和第二粘合构件并且与第一电路图案和第二电路图案电连接的通孔。