公开(公告)号：US20050242378A1

公开(公告)日：2005-11-03

申请号：US11175582

申请日：2005-07-06

Applicant: Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

Inventor： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/338 ,  H01L29/49 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC classification number: H01L29/66772 ,  H01L21/2807 ,  H01L29/4908

Abstract: A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

Abstract translation: 一种制造金属氧化物半导体器件结构的方法。 该方法包括通过离子注入将掺杂剂物质同时引入覆盖在半导体有源层上的绝缘层和栅电极的半导体有源层中。 选择半导体有源层的厚度，栅电极的厚度和掺杂剂物质的动能，使得半导体有源层和绝缘层中的掺杂剂物质的投影范围位于绝缘层内，并且投影 栅电极中的掺杂物种类的范围位于栅电极内。 结果，半导体有源层和栅电极可以在单个离子注入期间同时掺杂，而不需要另外的注入掩模。

公开(公告)号：US20050179029A1

公开(公告)日：2005-08-18

申请号：US10777576

申请日：2004-02-12

Applicant: Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

Inventor： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC: G11C13/02 ,  H01L21/336 ,  H01L27/28 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L29/06

CPC classification number: H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

Abstract: A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

Abstract translation: 一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。 所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。 栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。

公开(公告)号：US20050176197A1

公开(公告)日：2005-08-11

申请号：US10774827

申请日：2004-02-09

Applicant: Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

Inventor： Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

IPC: H01L21/8242

CPC classification number: H01L27/10867 ,  H01L27/10864

Abstract: A memory cell is formed for a memory cell array that is comprised of a plurality of the memory cells arranged in rows and columns. Deep trenches having sidewalls is formed within a semiconductor substrate. A buried plate region adjoining a deep trench is formed within the semiconductor substrate, and a dielectric film is formed along the sidewalls of the deep trench. A masking layer is patterned such that a portion of the dielectric film is covered by the masking layer and a remaining portion of the dielectric film is exposed. An upper region of the exposed portion of the dielectric film is removed such that a trench collar is formed along a middle portion of a side of the deep trench. The deep trench is partly filled with doped polysilicon. The dopants in the polysilicon diffuse through the side of the deep trench into adjoining regions of the semiconductor substrate during subsequent thermal processing steps to form a buried strap region along a side of the deep trench. The semiconductor substrate is patterned and etched to form at least one isolation trench that adjoins the isolation trench and two of the deep trenches and includes a buried strap region. The patterning uses a mask comprised of a lines and spaces pattern such that at least one active area is defined by the isolation trench and by the deep trench. Each of the lines and the spaces extends across the memory cell array.

Abstract translation: 为存储单元阵列形成存储单元，存储单元阵列由以行和列排列的多个存储单元组成。 具有侧壁的深沟槽形成在半导体衬底内。 在半导体衬底内形成与深沟槽相邻的掩埋板区域，沿着深沟槽的侧壁形成电介质膜。 图案化掩模层，使得电介质膜的一部分被掩蔽层覆盖，并且电介质膜的剩余部分被暴露。 去除电介质膜的暴露部分的上部区域，使得沿着深沟槽的一侧的中间部分形成沟槽套环。 深沟槽部分填充有掺杂多晶硅。 在随后的热处理步骤期间，多晶硅中的掺杂剂通过深沟槽的侧面扩散到半导体衬底的相邻区域中，以沿着深沟槽的一侧形成掩埋带区域。 对半导体衬底进行图案化和蚀刻以形成邻接隔离沟槽和两个深沟槽中的至少一个隔离沟槽并且包括掩埋带区域。 图案化使用由线和空间图案组成的掩模，使得至少一个有源区域由隔离沟槽和深沟槽限定。 每个行和空格都延伸穿过存储单元阵列。

公开(公告)号：US20050167655A1

公开(公告)日：2005-08-04

申请号：US10767065

申请日：2004-01-29

Applicant: Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

Inventor： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC: B82B1/00 ,  B82B3/00 ,  H01L27/28 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L29/06

CPC classification number: H01L51/057 ,  B82Y10/00 ,  H01L51/0048 ,  Y10S977/70 ,  Y10S977/734 ,  Y10S977/742

Abstract: Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

Abstract translation: 结合至少一个纳米管的垂直器件结构和通过化学气相沉积制造这种器件结构的方法。 每个纳米管通过由催化剂垫催化的化学气相沉积生长并且包裹在电介质材料的涂层中。 可以通过围绕封装的纳米管形成栅电极来形成垂直场效应晶体管，使得封装的纳米管垂直延伸穿过栅电极的厚度。 可以形成电容器，其中包裹的纳米管和带有封装的纳米管的相应的催化剂垫片形成一个电容器板。

公开(公告)号：US06890815B2

公开(公告)日：2005-05-10

申请号：US10655199

申请日：2003-09-04

Applicant: Johnathan Faltermeier ,  Jeremy Stephens ,  David Dobuzinsky ,  Larry Clevenger ,  Munir D. Naeem ,  Chienfan Yu ,  Larry Nesbit ,  Rama Divakaruni ,  Michael Maldei

Inventor： Johnathan Faltermeier ,  Jeremy Stephens ,  David Dobuzinsky ,  Larry Clevenger ,  Munir D. Naeem ,  Chienfan Yu ,  Larry Nesbit ,  Rama Divakaruni ,  Michael Maldei

IPC: H01L21/60 ,  H01L21/8242 ,  H01L29/76

CPC classification number: H01L27/10888 ,  H01L21/76897 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10891

Abstract: A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.

Abstract translation: 形成无边界接触的方法和用于半导体器件的无边界接触结构。 优选实施例包括使用设置在第一蚀刻选择性材料上的第二蚀刻选择性材料，以在半导体器件的各种材料层的蚀刻工艺期间保持第一蚀刻选择性材料，同时形成无边界接触。

公开(公告)号：US20050087875A1

公开(公告)日：2005-04-28

申请号：US10605766

申请日：2003-10-24

Applicant: Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

Inventor： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L29/40

CPC classification number: H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wiring-layer dielectric. A support is then formed that connects to the conductive structure, the support including an area thereunder. The wiring-layer dielectric is then removed from the area to form a gas dielectric.

Abstract translation: 在半导体器件结构上形成具有支撑结构的气体电介质的方法为半导体器件结构的导体提供低电容和足够的支撑。 在布线层电介质中形成诸如通孔或互连的导电结构。 然后形成连接到导电结构的支撑件，支撑件包括其下的区域。 然后从该区域去除布线层电介质以形成气体电介质。

公开(公告)号：US20060166432A1

公开(公告)日：2006-07-27

申请号：US10905881

申请日：2005-01-25

Applicant: Steven Holmes ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Larry Nesbit

Inventor： Steven Holmes ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Larry Nesbit

IPC: H01L21/8242

CPC classification number: H01L21/022 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/3165 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

Abstract: A process for forming a semiconductor device having an oxide beanie structure (an oxide cap overhanging an underlying portion of the device). An oxide layer is first provided covering that portion, with the layer having a top surface and a side surface. The top and side surfaces are then exposed to an oxide deposition bath, thereby causing deposition of oxide on those surfaces. Deposition of oxide on the top surface causes growth of the cap layer in a vertical direction and deposition of oxide on the side surface causes growth of the cap layer in a horizontal direction, thereby forming the beanie structure.

Abstract translation: 一种用于形成具有氧化物结构的氧化物半导体器件的方法（在器件的下面突出的氧化物盖）。 首先设置覆盖该部分的氧化物层，该层具有顶表面和侧表面。 然后将顶表面和侧表面暴露于氧化物沉积浴中，从而在这些表面上沉积氧化物。 顶部表面上的氧化物的沉积导致盖层在垂直方向上的生长，并且在侧面上的氧化物的沉积导致盖层在水平方向上的生长，从而形成豆瓣结构。

公开(公告)号：US20050130387A1

公开(公告)日：2005-06-16

申请号：US10732953

申请日：2003-12-11

Applicant: Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

Inventor： Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L27/01 ,  H01L21/76 ,  H01L31/0392

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L21/84

Abstract: To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

Abstract translation: 为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区 与氧化物。 通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。 此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。 因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过 其他氧化物区域。

公开(公告)号：US06790739B2

公开(公告)日：2004-09-14

申请号：US10249997

申请日：2003-05-27

Applicant: Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

Inventor： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

IPC: H01L2120

CPC classification number: H01L27/10894 ,  H01L21/76224 ,  H01L27/10861

Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

Abstract translation: 公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。 在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。 然而，支撑区域中的初始衬垫氮化物材料仍然保持。 然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

公开(公告)号：US20050202322A1

公开(公告)日：2005-09-15

申请号：US10798908

申请日：2004-03-11

Applicant: Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

Inventor： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC: G03C5/00 ,  G03F1/00 ,  G03F9/00

CPC classification number: G03F1/30

Abstract: Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.

Abstract translation: 用于制造用于半导体光刻系统中的交替相移掩模或掩模版的方法。 所述方法通常包括在手柄基板上形成一层相移掩模材料，并且图案化该层以限定凹陷的相移窗口。 图案层从手柄晶片转移到掩模板。 相移窗口的深度由相移掩模材料层的厚度确定，并且与图案化工艺无关。 特别地，相移窗口的深度不依赖于通过掩模板的表面的蚀刻工艺的蚀刻速率均匀性。