公开(公告)号：US07446395B2

公开(公告)日：2008-11-04

申请号：US11845888

申请日：2007-08-28

Applicant: Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha

Inventor： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha

IPC: H01L23/58

CPC classification number: H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/7842 ,  H01L29/7843

Abstract: The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a semiconductor device comprising a protective layer adjacent a first device, a first silicon nitride liner over the protective layer, a second silicon nitride liner adjacent a second device, and a first silicide layer adjacent the first device and a second silicide layer adjacent the second device, wherein a thickness is substantially the same in the first and second silicide layers.

Abstract translation: 本发明提供一种半导体器件，其具有双氮化物衬垫，硅化物层和位于氮化物衬底之下的保护层，用于防止蚀刻硅化物层。 本发明的第一方面提供一种半导体器件，其包括与第一器件相邻的保护层，保护层上的第一氮化硅衬垫，与第二器件相邻的第二氮化硅衬底以及与第一器件相邻的第一硅化物层和 第二硅化物层，其中第一和第二硅化物层中的厚度基本相同。

公开(公告)号：US20070292696A1

公开(公告)日：2007-12-20

申请号：US11845888

申请日：2007-08-28

Applicant: Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha

Inventor： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha

IPC: B32B9/04

CPC classification number: H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/7842 ,  H01L29/7843

Abstract: The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a semiconductor device comprising a protective layer adjacent a first device, a first silicon nitride liner over the protective layer, a second silicon nitride liner adjacent a second device, and a first silicide layer adjacent the first device and a second silicide layer adjacent the second device, wherein a thickness is substantially the same in the first and second silicide layers.

Abstract translation: 本发明提供一种半导体器件，其具有双氮化物衬垫，硅化物层和位于氮化物衬底之下的保护层，用于防止蚀刻硅化物层。 本发明的第一方面提供一种半导体器件，其包括与第一器件相邻的保护层，保护层上的第一氮化硅衬垫，与第二器件相邻的第二氮化硅衬底以及与第一器件相邻的第一硅化物层和 第二硅化物层，其中第一和第二硅化物层中的厚度基本相同。

公开(公告)号：US20060128086A1

公开(公告)日：2006-06-15

申请号：US10905024

申请日：2004-12-10

Applicant: Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha

Inventor： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha

IPC: H01L21/8238 ,  H01L21/31

CPC classification number: H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/7842 ,  H01L29/7843

Abstract: The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a protective layer to a device, applying a first silicon nitride liner to the device, removing a portion of the first silicon nitride liner, removing a portion of the protective layer, and applying a second silicon nitride liner to the device.

Abstract translation: 本发明提供一种半导体器件，其具有双氮化物衬垫，硅化物层和位于氮化物衬底之下的保护层，用于防止蚀刻硅化物层。 本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：向器件施加保护层，向器件施加第一氮化硅衬垫，去除第一氮化硅衬垫的一部分， 去除所述保护层的一部分，以及向所述装置施加第二氮化硅衬垫。

公开(公告)号：US20060110685A1

公开(公告)日：2006-05-25

申请号：US11329991

申请日：2006-01-10

Applicant: Wai-kin Li ,  Rajeev Malik ,  Joseph Mezzapelle

Inventor： Wai-kin Li ,  Rajeev Malik ,  Joseph Mezzapelle

IPC: G03F7/00

CPC classification number: G03F7/091 ,  G03F7/11 ,  Y10S430/151

Abstract: A process for prohibiting amino group transport from the top surface of a layered semiconductor wafer to a photoresist layer introduces a thin film oxynitride over the silicon nitride layer using a high temperature step of nitrous oxide (N2O) plus oxygen (O2) at approximately 300° C. for about 50 to 120 seconds. By oxidizing the silicon nitride layer, the roughness resulting from the adverse affects of amino group transport eliminated. Moreover, this high temperature step, non-plasma process can be used with the more advanced 193 nanometer technology, and is not limited to the 248 nanometer technology. A second method for exposing the silicon nitride layer to an oxidizing ambient, prior to the application of antireflective coating, introduces a mixture of N2H2 and oxygen (O2) ash at a temperature greater than or equal to 250° C. for approximately six minutes. This is followed by an O2 plasma clean and/or an Ozone clean, and then the subsequent layering of the ARC and photoresist.

Abstract translation: 用于禁止从层状半导体晶片的顶表面到光致抗蚀剂层的氨基转移的方法使用一氧化二氮（N 2 O 2 O）的高温步骤在氮化硅层上引入薄膜氧氮化物， 在约300℃下加氧气（O 2 H 2）约50至120秒。 通过氧化氮化硅层，消除了由氨基转移的不利影响产生的粗糙度。 此外，这种高温步骤，非等离子体工艺可以采用更先进的193纳米技术，并不限于248纳米技术。 在施加抗反射涂层之前，将氮化硅层暴露于氧化环境的第二种方法是引入N 2 H 2 O 2和氧的混合物（O _{2℃）灰分，温度大于或等于250℃约6分钟。 之后是等离子体清洁和/或臭氧清洁，然后再分层ARC和光致抗蚀剂。}

公开(公告)号：US06897107B2

公开(公告)日：2005-05-24

申请号：US10720490

申请日：2003-11-24

Applicant: Rama Divakaruni ,  Thomas W. Dyer ,  Rajeev Malik ,  Jack A. Mandelman ,  Venkatachajam C. Jaiprakash

Inventor： Rama Divakaruni ,  Thomas W. Dyer ,  Rajeev Malik ,  Jack A. Mandelman ,  Venkatachajam C. Jaiprakash

IPC: H01L21/316 ,  H01L21/318 ,  H01L21/8242 ,  H01L21/20

CPC classification number: H01L27/10864 ,  H01L21/31612 ,  H01L21/3185 ,  H01L27/10867

Abstract: A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.

Abstract translation: 在垂直MOSFET DRAM单元器件形成期间，能够在沟槽顶氧化物TTO（高密度等离子体）HDP沉积之前沉积薄氮化物衬垫的结构和方法。 随后在TTO侧壁蚀刻之后移除该衬垫。 该衬垫的一个功能是在TTO氧化物侧壁蚀刻期间保护套环氧化物不被蚀刻，并且通常提供在当前处理方案中未实现的横向蚀刻保护。 工艺顺序不依赖于以前沉积的膜用于套环保护，并且将TTO侧壁蚀刻保护与先前的处理步骤解耦以提供附加的工艺灵活性，例如在节点氮化物去除期间允许更薄的带切割掩模氮化物和更大的氮化物蚀刻和掩埋带 氮化界面去除。 有利地，在TTO之下的氮化物衬垫的存在降低了垂直MOSFET DRAM单元的栅极和电容器节点电极之间的TTO介质击穿的可能性，同时确保带扩散到栅极导体重叠。

公开(公告)号：US06794242B1

公开(公告)日：2004-09-21

申请号：US09675435

申请日：2000-09-29

Applicant: Thomas W. Dyer ,  Andreas Knorr ,  Laertis Economikos ,  Scott Halle ,  Rajeev Malik ,  Norbert Arnod

Inventor： Thomas W. Dyer ,  Andreas Knorr ,  Laertis Economikos ,  Scott Halle ,  Rajeev Malik ,  Norbert Arnod

IPC: H01L218242

CPC classification number: H01L27/10864 ,  H01L27/10891

Abstract: A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride remaining in place. Once the devices have been formed and the gate polysilicon has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide fills the regions between and on top of the polysilicon plugs. The Top Oxide is than planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.

Abstract translation: 如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。 顶部氧化物通过首先形成垂直装置而形成，其中衬垫氮化物保持就位。 一旦器件已经形成并且栅极多晶硅已经被平坦化到衬底氮化物的表面之下，衬垫氮化物被剥离掉，留下栅极多晶硅插塞的顶部延伸到活性硅表面之上。 这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。 沉积的顶部氧化物填充多晶硅插塞之间和之上的区域。 顶部氧化物被平坦化回到多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。 顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。

公开(公告)号：US06790739B2

公开(公告)日：2004-09-14

申请号：US10249997

申请日：2003-05-27

Applicant: Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

Inventor： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

IPC: H01L2120

CPC classification number: H01L27/10894 ,  H01L21/76224 ,  H01L27/10861

Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

Abstract translation: 公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。 在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。 然而，支撑区域中的初始衬垫氮化物材料仍然保持。 然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

公开(公告)号：US07348635B2

公开(公告)日：2008-03-25

申请号：US10905025

申请日：2004-12-10

Applicant: Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

Inventor： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

IPC: H01L31/00

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.

Abstract translation: 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个 第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

公开(公告)号：US20060128145A1

公开(公告)日：2006-06-15

申请号：US10905027

申请日：2004-12-10

Applicant: Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha

Inventor： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha

IPC: H01L21/44 ,  H01L21/8238

CPC classification number: H01L29/7842 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7843

Abstract: The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.

Abstract translation: 本发明提供一种具有双重氮化硅衬垫和重整硅化物层的半导体器件以及用于制造这种器件的相关方法。 重整的硅化物层的厚度和电阻基本上类似于未暴露于形成双重氮化硅衬里的硅化物层。 本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到硅化物层，去除第一氮化硅衬垫的一部分，重整硅化物层的一部分 在去除步骤期间去除，并且将第二氮化硅衬垫施加到硅化物层。

公开(公告)号：US07030012B2

公开(公告)日：2006-04-18

申请号：US10708530

申请日：2004-03-10

Applicant: Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Oh-Jung Kwon ,  Rajeev Malik

Inventor： Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Oh-Jung Kwon ,  Rajeev Malik

IPC: H01L21/44

CPC classification number: H01L27/10894 ,  H01L27/10861 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device including at least one semiconductor memory array region and logic circuits including a support region is formed by the following steps. Form a sacrificial polysilicon layer over the array region. Form a blanket gate oxide layer over the device. Form a thick deposit of polysilicon in both the array region where word lines are located and in the support region where the logic circuits are located. Remove the thick polysilicon layer, the gate oxide layer and the sacrificial polysilicon layer only in the array region. Then deposit a thin polysilicon layer in both the array region and support regions. Next deposit a metallic conductor coating including at least an elemental metal layer portion over the thin polysilicon layer. Then form word lines and sate electrodes in the array region and support region respectively.

Abstract translation: 包括至少一个半导体存储器阵列区域和包括支撑区域的逻辑电路的集成电路器件通过以下步骤形成。 在阵列区域上形成牺牲多晶硅层。 在器件上形成覆盖栅极氧化物层。 在字线位于的阵列区域和逻辑电路所在的支撑区域中形成厚多晶硅沉积物。 仅在阵列区域中去除厚的多晶硅层，栅极氧化物层和牺牲多晶硅层。 然后在阵列区域和支撑区域中沉积薄多晶硅层。 接着在薄多晶硅层上沉积至少包含元素金属层部分的金属导体涂层。 然后分别在阵列区域和支撑区域中形成字线和基极。