公开(公告)号：US20050189075A1

公开(公告)日：2005-09-01

申请号：US10789660

申请日：2004-02-27

Applicant: Shing-Chyang Pan ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Li-Lin Su ,  Shau-Lin Shue

Inventor： Shing-Chyang Pan ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Li-Lin Su ,  Shau-Lin Shue

IPC: B08B7/00 ,  H01J37/32 ,  H01L21/00 ,  C23F1/00

CPC classification number: H01L21/67109 ,  B08B7/0071 ,  H01J37/32862

Abstract: A reactive pre-clean chamber that contains a wafer heating apparatus, such as a high-temperature electrostatic chuck (HTESC), for directly heating a wafer supported on the apparatus during a pre-cleaning process. The wafer heating apparatus is capable of heating the wafer to the optimum temperatures required for a hydrogen plasma reactive pre-clean (RPC) process. Furthermore, degassing and pre-cleaning can be carried out in the same pre-clean chamber. The invention further includes a method of pre-cleaning a wafer using a pre-clean chamber that contains a wafer heating apparatus.

Abstract translation: 一种反应性预清洁室，其包含诸如高温静电卡盘（HTESC）的晶片加热装置，用于在预清洁过程期间直接加热支撑在装置上的晶片。 晶片加热装置能够将晶片加热到氢等离子体反应性预清洁（RPC）工艺所需的最佳温度。 此外，脱气和预清洁可以在相同的预清洁室中进行。 本发明还包括使用包含晶片加热装置的预清洁室预清洁晶片的方法。

公开(公告)号：US09136206B2

公开(公告)日：2015-09-15

申请号：US13557592

申请日：2012-07-25

Applicant: Li-Lin Su ,  Ching-Hua Hsieh ,  Huang-Ming Chen ,  Hsueh Wen Tsau

Inventor： Li-Lin Su ,  Ching-Hua Hsieh ,  Huang-Ming Chen ,  Hsueh Wen Tsau

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/485 ,  H01L29/49 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

Abstract translation: 一种器件包括一个包括一个底部的导电层和一个位于底部上的侧壁部分，其中侧壁部分连接到底部的一端。 含铝层与导电层的底部重叠，其中含铝层的顶表面与导电层的侧壁部分的顶部边缘基本平齐。 铝氧化物层覆盖含铝层。 含铜区域位于氧化铝层的上方，并且通过氧化铝层与含铝层隔开。 含铜区域通过导电层的侧壁部分的顶边缘电耦合到含铝层。

公开(公告)号：US20090209098A1

公开(公告)日：2009-08-20

申请号：US12031280

申请日：2008-02-14

Applicant: Li-Lin Su ,  Shing-Chyang Pan ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

Inventor： Li-Lin Su ,  Shing-Chyang Pan ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873

Abstract: A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber.

Abstract translation: 形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行第一沉积步骤以在第一室中形成种子层; 以及执行第一蚀刻步骤以去除种子层的一部分。 该方法还可以包括执行第二沉积步骤以增加种子层的厚度。 在与第一室不同的第二室中执行第一蚀刻步骤和第二沉积步骤中的至少一个。

公开(公告)号：US08252690B2

公开(公告)日：2012-08-28

申请号：US12031108

申请日：2008-02-14

Applicant: Li-Lin Su ,  Cheng-Lin Huang ,  Shing-Chyang Pan ,  Ching-Hua Hsieh

Inventor： Li-Lin Su ,  Cheng-Lin Huang ,  Shing-Chyang Pan ,  Ching-Hua Hsieh

IPC: H01L21/311

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873

Abstract: A method of forming a seed layer of an interconnect structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form the seed layer; and in-situ performing a first etch step to remove a portion of the seed layer. The method may further includes additional deposition and etch steps for forming the seed layer.

Abstract translation: 形成互连结构的籽晶层的方法包括形成介电层; 在介电层中形成开口; 执行第一沉积步骤以形成种子层; 并且原位执行第一蚀刻步骤以去除种子层的一部分。 该方法还可以包括用于形成种子层的附加沉积和蚀刻步骤。

公开(公告)号：US20090047780A1

公开(公告)日：2009-02-19

申请号：US12287516

申请日：2008-10-10

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

IPC: H01L21/44

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

Abstract: Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.

Abstract translation: 提供了一种形成复合阻挡层的方法，该复合阻挡层具有优异的阻挡性能，并且当复合阻挡层贯穿整个半导体器件时，两种电介质材料和导电材料具有优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常与电介质材料形成边界，并且结晶层通常与诸如互连材料的导电材料形成边界。

公开(公告)号：US20060027922A1

公开(公告)日：2006-02-09

申请号：US10909980

申请日：2004-08-03

Applicant: Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Cheng-Lin Huang ,  Li-Lin Su ,  Shau-Lin Shue

Inventor： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Cheng-Lin Huang ,  Li-Lin Su ,  Shau-Lin Shue

IPC: H01L23/48

CPC classification number: H01L21/76834 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.

Abstract translation: 一种具有包括第一金属元件的非导电盖层的半导体器件。 非导电盖层包括导电线上的第一金属氮化物，第一金属氧化物或第一金属氧氮化物，以及导电线之间的绝缘材料。 界面区域可以形成在导电线的顶表面上，界面区域包括盖层的金属元件。 盖层防止导电线中的导电材料迁移或扩散到相邻的随后形成的绝缘材料层中。 盖层也可以用作蚀刻停止层。

公开(公告)号：US08034709B2

公开(公告)日：2011-10-11

申请号：US12287516

申请日：2008-10-10

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

IPC: H01L21/4763

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

Abstract: Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.

Abstract translation: 提供了一种形成复合阻挡层的方法，该复合阻挡层具有优异的阻挡性能，并且当复合阻挡层贯穿整个半导体器件时，两种介电材料和导电材料具有优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常与电介质材料形成边界，并且结晶层通常与诸如互连材料的导电材料形成边界。

公开(公告)号：US20140027822A1

公开(公告)日：2014-01-30

申请号：US13557592

申请日：2012-07-25

Applicant: Li-Lin Su ,  Ching-Hua Hsieh ,  Huang-Ming Chen ,  Hsueh Wen Tsau

Inventor： Li-Lin Su ,  Ching-Hua Hsieh ,  Huang-Ming Chen ,  Hsueh Wen Tsau

IPC: H01L23/485 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

Abstract translation: 一种器件包括一个包括一个底部的导电层和一个位于底部上的侧壁部分，其中侧壁部分连接到底部的一端。 含铝层与导电层的底部重叠，其中含铝层的顶表面与导电层的侧壁部分的顶部边缘基本平齐。 铝氧化物层覆盖含铝层。 含铜区域位于氧化铝层的上方，并且通过氧化铝层与含铝层隔开。 含铜区域通过导电层的侧壁部分的顶边缘电耦合到含铝层。

公开(公告)号：US07704886B2

公开(公告)日：2010-04-27

申请号：US12031280

申请日：2008-02-14

Applicant: Li-Lin Su ,  Shing-Chyang Pan ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

Inventor： Li-Lin Su ,  Shing-Chyang Pan ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873

Abstract: A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber.

Abstract translation: 形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行第一沉积步骤以在第一室中形成种子层; 以及执行第一蚀刻步骤以去除种子层的一部分。 该方法还可以包括执行第二沉积步骤以增加种子层的厚度。 在与第一室不同的第二室中执行第一蚀刻步骤和第二沉积步骤中的至少一个。

公开(公告)号：US20090209106A1

公开(公告)日：2009-08-20

申请号：US12031108

申请日：2008-02-14

Applicant: Li-Lin Su ,  Cheng-Lin Huang ,  Shing-Chyang Pan ,  Ching-Hua Hsieh

Inventor： Li-Lin Su ,  Cheng-Lin Huang ,  Shing-Chyang Pan ,  Ching-Hua Hsieh

IPC: H01L21/311

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873

Abstract: A method of forming a seed layer of an interconnect structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form the seed layer; and in-situ performing a first etch step to remove a portion of the seed layer. The method may further includes additional deposition and etch steps for forming the seed layer.

Abstract translation: 形成互连结构的籽晶层的方法包括形成介电层; 在介电层中形成开口; 执行第一沉积步骤以形成种子层; 并且原位执行第一蚀刻步骤以去除种子层的一部分。 该方法还可以包括用于形成种子层的附加沉积和蚀刻步骤。