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    Integrated circuit having a gate oxide
    8.
    发明授权
    Integrated circuit having a gate oxide 失效
    具有栅极氧化物的集成电路

    公开(公告)号：US5654863A

    公开(公告)日：1997-08-05

    申请号：US744684

    申请日：1996-11-07

    Applicant: Neil Davies

    Inventor： Neil Davies

    IPC: H01L27/04 ,  G01R31/26 ,  G01R31/28 ,  H01L21/82 ,  H01L21/822 ,  H01L27/02 ,  H01L29/866 ,  H02H9/04

    CPC classification number: G01R31/2884 ,  G01R31/2621 ,  H01L27/0251

    Abstract: An integrated circuit having a gate oxide, preferably for a DMOS circuit having a protective device against electrostatic overvoltages (ESD), is to connect a limiting circuit in series with the protective device. This series circuit means that, during the wafer production, an increased voltage can be applied to the gate of the integrated circuit, for testing the gate oxide, without the circuit being limited to a lower value. After testing, the limiting circuit is connected irreversibly in its low-resistance state, with the result that subsequent ESD interference voltages are limited by the built-in protective device. A zener zapping diode is provided as the limiting circuit. An advantageous result of the arrangement is the fact that an additional bonding connection for connecting the gate connection to the protective device is no longer necessary.

    Abstract translation: 具有栅极氧化物的集成电路，优选用于具有防静电过电压（ESD）的保护装置的DMOS电路，是将限制电路与保护装置串联连接。 该串联电路意味着，在晶片生产期间，可以向集成电路的栅极施加增加的电压，用于测试栅极氧化物，而不将电路限制在较低的值。 测试后，限制电路在其低电阻状态下不可逆地连接，结果是后续ESD干扰电压受到内置保护装置的限制。 提供齐纳二极管作为限制电路。 该布置的有利结果是不再需要用于将栅极连接连接到保护装置的附加接合连接。

    Monolithically integrated circuit
    9.
    发明授权
    Monolithically integrated circuit 失效
    单片集成电路

    公开(公告)号：US5432371A

    公开(公告)日：1995-07-11

    申请号：US167839

    申请日：1993-12-20

    Applicant: Volkmar Denner ,  Wolfgang Troelenberg ,  Peter Brauchle ,  William-Neil Fox ,  Neil Davies

    Inventor： Volkmar Denner ,  Wolfgang Troelenberg ,  Peter Brauchle ,  William-Neil Fox ,  Neil Davies

    IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78

    CPC classification number: H01L29/7803 ,  H01L27/0251 ,  H01L2924/0002

    Abstract: A monolithically integrated circuit arrangement is arranged in a disc-shaped monocrystalline semiconductor body (100) of a first conductivity type, which semiconductor body consists of silicon and has a first and second main surface. The monolithically integrated circuit arrangement contains a vertical MOSFET power transistor (T1) which consists of a plurality of partial transistors connected in parallel and surrounded by a guard ring (4) of a second conductivity type opposite that of the semiconductor body (100). Proceeding from the first main surface (13), at least one zone (7, 8) of the conductivity type of the semiconductor body (100) but of increased impurity concentration is diffused into the guard ring (4) so as to form at least one active and/or passive peripheral circuit element (T2) which has a protective and/or regulating and/or control function.

    Abstract translation: PCT No.PCT / DE92 / 00479 Sec。 371日期：1993年12月20日 102（e）日期1993年12月20日PCT提交1992年6月10日PCT公布。 公开号WO93 / 00709 日期：1993年1月7日。单片集成电路布置在第一导电类型的盘状单晶体半导体本体（100）中，该半导体主体由硅组成并具有第一和第二主表面。 单片集成电路装置包括垂直MOSFET功率晶体管（T1），其由并联连接并由与半导体本体（100）相反的第二导电类型的保护环（4）包围的多个部分晶体管组成。 从第一主表面（13）开始，半导体主体（100）的导电类型的至少一个区域（7,8）扩散到保护环（4）中，以至少形成 具有保护和/或调节和/或控制功能的一个有源和/或无源外围电路元件（T2）。

    Sensor and method for the manufacture thereof
    10.
    发明申请
    Sensor and method for the manufacture thereof 有权
    传感器及其制造方法

    公开(公告)号：US20100140618A1

    公开(公告)日：2010-06-10

    申请号：US12590585

    申请日：2009-11-10

    Applicant: Jochen Reinmuth ,  Neil Davies ,  Simon Armbruster ,  Ando Feyh

    Inventor： Jochen Reinmuth ,  Neil Davies ,  Simon Armbruster ,  Ando Feyh

    IPC: H01L31/103 ,  H01L31/18

    CPC classification number: G01J5/20 ,  G01J5/08 ,  G01J5/0853 ,  H01L27/14649

    Abstract: A sensor includes at least one micro-patterned diode pixel that has a diode implemented in, on, or under a diaphragm, and the diaphragm in turn being implemented above a cavity. The diode is contacted via supply leads that are implemented at least in part in, on, or under the diaphragm, and the diode is implemented in a polycrystalline semiconductor layer. The diode is implemented by way of two low-doped diode regions or at least one low-doped diode region. At least parts of the supply leads are implemented by way of highly doped supply lead regions of the shared polycrystalline semiconductor layer.

    Abstract translation: 传感器包括至少一个微图案化的二极管像素，其具有在隔膜内，上或下面实现的二极管，并且隔膜依次在空腔上方实现。 二极管通过至少部分地在隔膜中，上或下面实现的电源引线接触，并且二极管实现在多晶半导体层中。 二极管通过两个低掺杂二极管区域或至少一个低掺杂二极管区域实现。 供电线的至少一部分通过共享多晶半导体层的高掺杂电源引线区实现。

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