公开(公告)号：US06197641B1

公开(公告)日：2001-03-06

申请号：US09335707

申请日：1999-06-18

Applicant: John Michael Hergenrother ,  Donald Paul Monroe ,  Gary Robert Weber

Inventor： John Michael Hergenrother ,  Donald Paul Monroe ,  Gary Robert Weber

IPC: H01L21336

CPC classification number: H01L29/66666 ,  H01L29/161 ,  H01L29/7827 ,  H01L29/78642

Abstract: A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.

Abstract translation: 公开了用于制造用于集成电路的垂直MOSFET器件的工艺。 在该过程中，在半导体衬底上依次形成至少三层材料。 三层被布置成使得第二层介于第一层和第三层之间。 第二层是牺牲性的，即在随后的处理期间该层被完全去除。 第二层的厚度限定了垂直MOSFET的物理栅极长度。 在该过程中，第一层和第三层的蚀刻速率明显低于蚀刻剂中被选择去除第二层的第二层的蚀刻速率。 顶层，其是第三层或后续层，是用于随后执行的机械抛光步骤的停止层，其用于去除在至少三层上形成的材料。 在衬底上形成至少三层材料之后，在这些层中形成窗口或沟槽。 窗口终止于在硅衬底中形成源区或漏区之一的硅衬底的表面。 然后用半导体材料填充窗口或沟槽。 该半导体插头成为晶体管的垂直沟道。 因此，晶体半导体插头被掺杂以在插头中形成源延伸部，漏极延伸部和沟道区域。 随后的处理形成垂直通道顶部的源极或漏极中的另一个，并去除牺牲的第二材料层。 牺牲第二层的去除暴露了掺杂半导体插件的一部分。 然后在掺杂半导体插头的暴露部分上形成器件栅极电介质。 然后沉积栅电极。 所得装置的物理栅极长度对应于第二材料层的沉积厚度。

公开(公告)号：US07237259B2

公开(公告)日：2007-06-26

申请号：US10289942

申请日：2002-11-07

Applicant: Paul Monroe Crutcher ,  Paul Maurice Gunsch ,  Todd Douglas Inman ,  William Russell Marshall

Inventor： Paul Monroe Crutcher ,  Paul Maurice Gunsch ,  Todd Douglas Inman ,  William Russell Marshall

IPC: G06F15/16 ,  G06F17/00 ,  G06F9/00

CPC classification number: H04L63/02 ,  H04L63/20

Abstract: Disclosed are two mechanisms for preventing access failures attributable to dynamic port assignment of firewall-blocked ports. The mechanism involves an enhanced firewall that opens blocked ports prior to possible dynamic allocation so that the blocked ports are not available when a port is requested. The second mechanism involves an enhanced commutations stack that works in conjunction with an enhanced firewall to reserve blocked ports so that the blocked ports are not available for dynamic allocation when a port is requested.

Abstract translation: 公开了两种用于防止归因于防火墙阻塞端口的动态端口分配的接入故障的机制。 该机制涉及增强的防火墙，在可能的动态分配之前打开阻塞的端口，以便在请求端口时阻塞的端口不可用。 第二种机制涉及一种增强的换向堆栈，与增强型防火墙配合使用，以保留阻塞的端口，以便在请求端口时阻塞的端口不可用于动态分配。

公开(公告)号：US06903411B1

公开(公告)日：2005-06-07

申请号：US09648164

申请日：2000-08-25

Applicant: Yih-Feng Chyan ,  John Michael Hergenrother ,  Donald Paul Monroe

Inventor： Yih-Feng Chyan ,  John Michael Hergenrother ,  Donald Paul Monroe

IPC: H01L27/10 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L29/78 ,  H01L29/778

CPC classification number: H01L29/66666 ,  H01L21/76895 ,  H01L21/823885 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7827

Abstract: An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region.In another embodiment a first device region, is formed on a semiconductor layer. A second device region, is also formed on the semiconductor layer. A conductor layer comprising metal is positioned adjacent the first and second device regions to effect electrical connection between the first and second device regions. A first field effect transistor gate region is formed over the first device region and the conductor layer and a second field effect transistor gate region is formed over the second device region and the conductor layer.

Abstract translation: 用于在半导体层中或邻近半导体层之间的区域之间连接的架构。 根据一个实施例，半导体器件包括第一层半导体材料和第一场效应晶体管，其具有形成在第一层中的第一源/漏区。 在第一层上形成晶体管的沟道区，并且在沟道区上形成相关联的第二源极/漏极区。 该器件包括第二场效应晶体管，其还具有形成在第一层中的第一源/漏区。 在第一层上形成第二晶体管的沟道区，并且在沟道区上形成相关联的第二源极/漏极区。 包括金属的导电层位于每个晶体管的第一源极/漏极区之间，以将电流从一个第一源极/漏极区传导到另一个第一源极/漏极区。 在另一个实施例中，第一器件区域形成在半导体层上。 第二器件区域也形成在半导体层上。 包括金属的导体层定位成邻近第一和第二器件区域以实现第一和第二器件区域之间的电连接。 第一场效应晶体管栅极区域形成在第一器件区域上，并且导体层和第二场效应晶体管栅极区域形成在第二器件区域和导体层上。

公开(公告)号：US20160031275A1

公开(公告)日：2016-02-04

申请号：US14449963

申请日：2014-08-01

Applicant: Paul MONROE ,  Devin WORK

Inventor： Paul MONROE ,  Devin WORK

IPC: B60F3/00 ,  B64C39/02 ,  B64C27/32

CPC classification number: B60F3/0007 ,  B60F3/003 ,  B63G8/001 ,  B64C37/00 ,  B64C39/024 ,  B64C2201/024 ,  B64C2201/108 ,  B64C2201/12 ,  B64C2201/165 ,  B64C2201/18

Abstract: Vehicle for aeronautic operation and submersed operation includes members secured to rotors and a body, the members having adjustable features arranged and disposed to position the rotors to rotate in a first plane during the aeronautic operation and a second plane during the submersed operation, a fluid enclosure operably connected through the body to the rotor, the fluid enclosure having a submersion mechanism arranged and disposed for the vehicle to adjustably ascend and descend during the submersed operation of the vehicle, and a control system and power system for operably controlling the rotor, the adjustable feature, and/or the fluid enclosure. The rotor is configured to move the vehicle during the aeronautic operation and the submersed operation. A process includes operating the vehicle in the aeronautic operation and the submersed operation.

Abstract translation: 用于航空操作和浸没操作的车辆包括固定到转子和主体的构件，所述构件具有可调整的特征，其布置和设置成在转向器的运行期间在第一平面中定位转子并且在浸没操作期间具有第二平面， 可操作地通过本体连接到转子，流体外壳具有布置和设置用于车辆在潜入式操作期间可调节地上升和下降的浸入机构，以及用于可操作地控制转子的控制系统和动力系统， 特征和/或流体外壳。 转子构造成在航空操作和浸没操作期间移动车辆。 一个过程包括在航空操作和潜水操作中操作车辆。

公开(公告)号：US4882564A

公开(公告)日：1989-11-21

申请号：US202199

申请日：1988-06-06

Applicant: Paul Monroe ,  James Kurth

Inventor： Paul Monroe ,  James Kurth

IPC: B60H1/00 ,  G01K1/02 ,  G01K3/00 ,  G05D23/19

CPC classification number: G05D23/1905 ,  B60H1/00978 ,  G01K1/024 ,  G01K3/005

Abstract: A remote temperature sensing and warning system for a temperature controlled vehicle comprising a remote temperature sensing unit for measuring the temperature in the transport container and transmitting the temperature signal within a repeating time frame through the existing vehicle wiring to a remote receiver; the receiver decoding and converting the signal into a displayable form to continuously display the current temperature of the transport container; the receiver further detecting out of range temperatures and signal transmission errors and providing visual and aural alarms therefrom.

Abstract translation: 一种用于温度控制车辆的远程温度感测和警报系统，包括用于测量运输容器中的温度的远程温度感测单元，并且通过现有车辆布线将重复时间范围内的温度信号传送到远程接收器; 接收机将信号解码并转换成可显示形式，以连续显示运送容器的当前温度; 接收器进一步检测超出范围的温度和信号传输错误，并从中提供视觉和听觉警报。

公开(公告)号：US06653181B2

公开(公告)日：2003-11-25

申请号：US10211674

申请日：2002-08-02

Applicant: John Michael Hergenrother ,  Donald Paul Monroe

Inventor： John Michael Hergenrother ,  Donald Paul Monroe

IPC: H01L218238

CPC classification number: H01L21/823885 ,  H01L27/0688 ,  H01L27/092

Abstract: A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices. After the at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form an n-type region and a p-type region in the structure. Windows or trenches are formed in the layers in both the n-type region and the p-type region. The windows terminate at the surface of the silicon substrate in which one of either a source or drain region is formed. The windows or trenches are then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.

Abstract translation: 公开了一种用于制造具有垂直MOSFET器件的CMOS集成电路的工艺。 在该过程中，在半导体衬底上依次形成至少三层材料。 三层被布置成使得第二层介于第一层和第三层之间。 第二层是牺牲性的，即在随后的处理期间该层被完全去除。 第二层的厚度限定了垂直MOSFET器件的物理栅极长度。 在衬底上形成至少三层材料之后，所得结构被选择性地掺杂以在该结构中形成n型区域和p型区域。 Windows或沟槽形成在n型区域和p型区域中的层中。 窗口终止于其中形成源极或漏极区域之一的硅衬底的表面。 然后用半导体材料填充窗口或沟槽。 该半导体插头成为晶体管的垂直沟道。 因此，晶体半导体插头被掺杂以在插头中形成源延伸部，漏极延伸部和沟道区域。 随后的处理形成垂直通道顶部的源极或漏极中的另一个，并去除牺牲的第二材料层。 牺牲第二层的去除暴露了掺杂半导体插件的一部分。 然后在掺杂半导体插头的暴露部分上形成器件栅极电介质。 然后沉积栅电极。 所得装置的物理栅极长度对应于第二材料层的沉积厚度。

公开(公告)号：US5800461A

公开(公告)日：1998-09-01

申请号：US538831

申请日：1995-11-13

Applicant: John Menken ,  Paul Monroe

Inventor： John Menken ,  Paul Monroe

IPC: A61N1/37 ,  A61N1/39

CPC classification number: A61N1/3925 ,  A61N1/37 ,  A61N1/3975

Abstract: A capacitor charging circuit for charging a defibrillation capacitor in a constant period of time regardless of battery voltage by employing a controlled duty cycle charging technique. The defibrillation capacitor is charged in a piecemeal manner through a transistor and flyback transformer circuit. The gate of the transistor is driven by a constant frequency pulse train inverter drive signal in which voltage is conveyed to the capacitors during one-half of the full cycle of the pulse train. The primary of the transformer is controlled by each pulse of the inverter drive signal so that the secondary of the transformer supplies current to the defibrillation capacitors during the off half cycle of the drive signal, the charge being built up in the defibrillation capacitors incrementally during the off half cycle of the inverter drive signal until the predetermined voltage is reached.

Abstract translation: 一种电容器充电电路，其通过采用受控的占空比充电技术而与电池电压无关地在恒定时间段内对除颤电容器充电。 除颤电容器通过晶体管和反激式变压器电路分段充电。 晶体管的栅极由恒定频率脉冲串逆变器驱动信号驱动，其中在脉冲串的整个周期的一半期间电压被传送到电容器。 变压器的主要部分由逆变器驱动信号的每个脉冲控制，使得变压器的次级在驱动信号的关闭半周期期间向除颤电容器提供电流，在除颤电容器内逐渐积累电荷 关闭逆变器驱动信号的半周期，直到达到预定电压。

公开(公告)号：US5443065A

公开(公告)日：1995-08-22

申请号：US175498

申请日：1993-12-30

Applicant: Gene Berghoff ,  Scott Latterell ,  Paul Monroe

Inventor： Gene Berghoff ,  Scott Latterell ,  Paul Monroe

IPC: A61N1/362 ,  A61N1/372 ,  A61B5/04

CPC classification number: A61N1/37211 ,  A61N1/3625

Abstract: A temporary pacemaker combines technologies of the implantable pacemaker, the waterproof watch, with a separate remote-control programming unit that communicates with the pacemaker via IR radiation. An LCD readout on the temporary pacemaker continuously reports on current settings, and is monitored periodically, as well as during the setting process. The programming unit is aimed at an IR sensor on the pacemaker, and its dedicated controls are used for setting, with the aid of prompting messages on its own LCD panel. Battery life is about 6-9 months, while that for the lithium battery in the sealed and sterilizable pacemaker approaches five years.A multi-conductor connector and an adapter for use with a temporary external pacemaker, is disclosed which reduces the complexity of connecting temporary pacing leads, adapters, extension cables, heart wires or other miscellaneous cables to a pacing device. It also reduces the possibility of inadvertent removal/disconnection of these patient connected cable systems, and yet allows for a quick release.

Abstract translation: 临时起搏器将植入式起搏器，防水手表的技术与通过红外辐射与起搏器通信的单独的遥控编程单元相结合。 临时起搏器上的LCD读数器会持续报告当前设置，并定期监控以及设置过程。 编程单元针对起搏器上的红外传感器，其专用控制器用于借助于在自己的LCD面板上提示消息进行设置。 电池寿命约6-9个月，而密封和消毒起搏器中锂电池的使用寿命接近五年。 公开了一种用于临时外部起搏器的多导体连接器和适配器，其降低将临时起搏引线，适配器，延长电缆，心脏线或其他杂项电缆连接到起搏装置的复杂性。 这也降低了这些患者连接的电缆系统的意外移除/断开的可能性，并且允许快速释放。

公开(公告)号：US20150369529A1

公开(公告)日：2015-12-24

申请号：US14307810

申请日：2014-06-18

Applicant: Jon Paul Monroe

Inventor： Jon Paul Monroe

IPC: F25D3/08 ,  F25D23/04 ,  F25D25/00 ,  F25D23/02

CPC classification number: F25D3/08 ,  F25D23/069 ,  F25D2303/08221 ,  F25D2303/0843

Abstract: A compartmentalized cooler is provided. The cooler may have partitions capable of isolating different compartments of the cooler from the other. These partitions may have additional functions such as acting as a cutting board or ice pack. The cooler may further have a lock box contained within one of the partitions.

Abstract translation: 提供了分隔式冷却器。 冷却器可以具有能够将冷却器的不同隔室与另一个隔离的隔板。 这些隔板可能具有额外的功能，例如用作砧板或冰袋。 冷却器还可以具有包含在一个隔板内的锁箱。

公开(公告)号：US6027975A

公开(公告)日：2000-02-22

申请号：US143274

申请日：1998-08-28

Applicant: John M. Hergenrother ,  Donald Paul Monroe

Inventor： John M. Hergenrother ,  Donald Paul Monroe

IPC: H01L21/336 ,  H01L29/161 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66666 ,  H01L29/161 ,  H01L29/7827 ,  H01L29/78642

Abstract: A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer.After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.

Abstract translation: 公开了用于制造用于集成电路的垂直MOSFET器件的工艺。 在该过程中，在半导体衬底上依次形成至少三层材料。 三层被布置成使得第二层介于第一层和第三层之间。 第二层是牺牲性的，即在随后的处理期间该层被完全去除。 第二层的厚度限定了垂直MOSFET的物理栅极长度。 在该过程中，第一层和第三层的蚀刻速率明显低于蚀刻剂中被选择去除第二层的第二层的蚀刻速率。 在衬底上形成至少三层材料之后，在这些层中形成窗口或沟槽。 窗口终止于在硅衬底中形成源区或漏区之一的硅衬底的表面。 然后用半导体材料填充窗口或沟槽。 该半导体插头成为晶体管的垂直沟道。 因此，晶体半导体插头被掺杂以在插头中形成源延伸部，漏极延伸部和沟道区域。 随后的处理形成垂直通道顶部的源极或漏极中的另一个，并去除牺牲的第二材料层。 牺牲第二层的去除暴露了掺杂半导体插件的一部分。 然后在掺杂半导体插头的暴露部分上形成器件栅极电介质。 然后沉积栅电极。 所得装置的物理栅极长度对应于第二材料层的沉积厚度。