公开(公告)号：US07143315B2

公开(公告)日：2006-11-28

申请号：US10688487

申请日：2003-10-16

Applicant: Robert A. Rust ,  Barry J. Oldfield ,  Steven Lee Shrader ,  Christine Grund ,  Christopher W. Johansson

Inventor： Robert A. Rust ,  Barry J. Oldfield ,  Steven Lee Shrader ,  Christine Grund ,  Christopher W. Johansson

IPC: G06F11/00

CPC classification number: G06F11/004

Abstract: Fault tolerant data storage systems and methods of operating a fault tolerant data storage system are presented. In one aspect of the invention, a fault tolerant data storage system comprises: a plurality of coupled components individually including: an interface adapted to couple with a data connection and to selectively receive a plurality of transactions from the data connection; transaction processing circuitry coupled with the interface and configured to process transactions received from the interface; and analysis circuitry configured to detect error conditions within the transactions and to prevent entry of transactions individually including an error condition into the respective component responsive to the detection.

Abstract translation: 介绍了容错数据存储系统和操作容错数据存储系统的方法。 在本发明的一个方面，容错数据存储系统包括：多个耦合组件，其分别包括：适于与数据连接耦合并且有选择地从所述数据连接接收多个事务的接口; 与所述接口耦合并被配置为处理从所述接口接收的事务的事务处理电路; 以及分析电路，其被配置为检测所述事务内的错误状况，并且防止响应于所述检测而单独地将包括错误状况的事务进入各个部件。

公开(公告)号：US06661334B1

公开(公告)日：2003-12-09

申请号：US09678601

申请日：2000-09-26

Applicant: Thomas W Ives ,  Robert A. Rust ,  Barry J Oldfield

Inventor： Thomas W Ives ,  Robert A. Rust ,  Barry J Oldfield

IPC: G05B1900

CPC classification number: G05B19/128 ,  G05B19/048 ,  G05B2219/21076 ,  G11B33/124

Abstract: A verification system for an interchangeable component configured to be mated with a receiving system. The system includes a key device supported by the interchangeable component. The key device includes a transmitter configured to transmit a signal comprising component identification characteristics. The system further includes a lock system having a signal receiver and a verification component. The signal receiver is configured to receive the signal from the key device transmitter and pass the signal to the verification component. The verification component is configured to use the signal to determine whether or not the component should be admitted to the receiving system, and to generate an authorization signal if the component should be admitted.

Abstract translation: 用于可配置成与接收系统配合的可互换组件的验证系统。 该系统包括由可互换组件支持的关键设备。 关键装置包括被配置为发射包括部件识别特性的信号的发射机。 该系统还包括具有信号接收器和验证部件的锁定系统。 信号接收器被配置为从密钥设备发射机接收信号，并将信号传递给验证部件。 验证组件被配置为使用该信号来确定组件是否应该被允许进入接收系统，并且如果组件应该被允许，则生成授权信号。

公开(公告)号：US06622285B1

公开(公告)日：2003-09-16

申请号：US09706315

申请日：2000-11-02

Applicant: Robert A. Rust ,  Barry J Oldfield

Inventor： Robert A. Rust ,  Barry J Oldfield

IPC: G06F1100

CPC classification number: G06F11/0727 ,  G06F11/079

Abstract: Methods and systems for fault location are described. In one described embodiment, an “in circuit” solution is provided for locating faults along a passive transmission line. Once a fault occurs, various hardware gathers information that is necessary to determine which of a number of different replaceable components has failed. This enables the subsystem to properly respond to the fault condition and thereby eliminate any guessing that could potentially lead to loss of data availability. In the particular described embodiment, signals are driven and received through a selected input/output (I/O) pad. Logic circuitry is provided and launches a wave onto the passive transmission line. Immediately following the launching of the wave, the I/O pad is monitored and can sense the reflections from the wave that has just been launched. By analyzing the reflections, and more specifically the time that it takes for the reflection to be sensed, a determination is made as to the fault location. Once the fault location (or distance thereto) is ascertained, a determination can be made as to which component has failed. At this point, an intelligent decision can be made as to which component should continue operation.

Abstract translation: 描述故障定位的方法和系统。 在一个描述的实施例中，提供了一种“在线”解决方案，用于沿着被动传输线定位故障。 一旦发生故障，各种硬件收集必要的信息，以确定多个不同的可替换组件中的哪一个已经失败。 这使得子系统能够对故障状况进行适当的响应，从而消除可能导致数据可用性损失的任何猜测。 在具体描述的实施例中，通过所选择的输入/输出（I / O）焊盘来驱动和接收信号。 提供逻辑电路，并在无源传输线上发射波。 在发射波浪之后，I / O板被监控，并且可以感测刚刚发射的波形的反射。 通过分析反射，更准确地说，检测反射所需的时间，就确定了故障位置。 一旦确定了故障位置（或其距离），就可以确定哪个部件已经失败。 在这一点上，可以做出关于哪个组件应该继续运行的智能决定。

公开(公告)号：US06230240B1

公开(公告)日：2001-05-08

申请号：US09103329

申请日：1998-06-23

Applicant: Steven L. Shrader ,  Robert A. Rust

Inventor： Steven L. Shrader ,  Robert A. Rust

IPC: G06F1300

CPC classification number: G06F11/2097 ,  G06F3/0607 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0689 ,  G06F11/2089 ,  G06F2201/82 ,  G11B20/10

Abstract: A storage management system for a Redundant Array of Independent Disks (RAID) data storage system and an AutoRAID memory transaction manager for a disk array controller are disclosed. The disk array controller enables a consistent, coherent memory image of the data storage space to all processors across hot-plug interfaces. To external processes seeking to read or write data, the memory image looks the same across the hot-plug interface. The disk array controller has two identical controllers, each with its own non-volatile memory, to maintain redundant images of disk array storage space. A hot-plug interface interconnects the two controllers. Each controller has an AutoRAID memory transaction manager that enables sharing of cyclic redundancy check (CRC)-protected memory transactions over the hot-plug interface between the two controllers. The AutoRAID memory transaction managers also have transaction queues which facilitate ordered execution of the memory transactions regardless of which controller originated the transactions. The AutoRAID transaction manager includes first and second bus interfaces, a mirror entity, and a local memory interface. Mirrored read and write transactions are handled atomically across the hot-plug interface.

Abstract translation: 公开了用于磁盘阵列控制器的独立磁盘冗余阵列（RAID）数据存储系统和AutoRAID存储器事务管理器的存储管理系统。 磁盘阵列控制器可以实现热插拔接口上所有处理器的数据存储空间的一致，一致的内存映像。 对于寻求读取或写入数据的外部进程，内存映像在热插拔接口中看起来相同。 磁盘阵列控制器具有两个相同的控制器，每个都具有自己的非易失性存储器，以保持磁盘阵列存储空间的冗余映像。 热插拔接口互连两个控制器。 每个控制器都有一个AutoRAID内存事务管理器，可以通过两个控制器之间的热插拔接口共享循环冗余校验（CRC）保护的内存事务。 AutoRAID内存事务管理器还具有事务队列，便于有序执行内存事务，无论哪个控制器发起事务。 AutoRAID事务管理器包括第一和第二总线接口，镜像实体和本地存储器接口。 镜像读写事务在热插拔接口上以原子方式处理。

公开(公告)号：US5886655A

公开(公告)日：1999-03-23

申请号：US833776

申请日：1997-04-09

Applicant: Robert A. Rust

Inventor： Robert A. Rust

IPC: G06T9/00 ,  H03M7/40 ,  H03M7/00

CPC classification number: H03M7/4006

Abstract: The present invention provides improved compression ratios for small data sets with only a minor impact of the compression ration of larger data sets by rapidly tracking the statistics at the beginning of the compression run, slowing down to a traditional pace as the size increases. This is accomplished by limiting the size of the probability table at the start. As more data passes through the compressor, the size of the table is expanded. The size of the probability is controlled by gradually opening the context window for limited number of bytes at the beginning of the data set.

Abstract translation: 本发明通过快速跟踪在压缩运行开始时的统计数据，随着尺寸的增加而减慢到传统的步伐，为小数据集提供了改进的压缩比，其中只有较大数据集的压缩比的影响较小。 这通过在开始时限制概率表的大小来实现。 随着越来越多的数据通过压缩机，表的尺寸就会扩大。 概率的大小是通过在数据集开始时逐渐打开有限数量的字节的上下文窗口来控制的。

公开(公告)号：US5880688A

公开(公告)日：1999-03-09

申请号：US832681

申请日：1997-04-09

Applicant: Robert A. Rust

Inventor： Robert A. Rust

IPC: B41J5/44 ,  G06T9/00 ,  H03M7/40 ,  H03M7/00

CPC classification number: H03M7/4006 ,  G06T9/005

Abstract: The present invention provides improved compression ratios for small data sets with only a minor impact of the compression ration of larger data sets by selecting a context model optimized for the size of the data set being processed. The size of the original data is determined. Based on the size, a context model is selected. The original data is compressed into the compressed data using the context model. Any number of context models may be defined and appropriate values chosen. To decompress, it is necessary to select a context model based on the size of the original data. Two ways of detecting the correct context model are described. First, the size of the original data is part of the compressed data. Alternatively, an indicator, identifying which context model was used to compress the original data, is part the compressed data.

Abstract translation: 本发明通过选择针对正在处理的数据集的大小而优化的上下文模型，为较小数据集提供了改进的压缩比，只对较大数据集的压缩比进行较小的影响。 确定原始数据的大小。 基于大小，选择上下文模型。 使用上下文模型将原始数据压缩成压缩数据。 可以定义任意数量的上下文模型，并选择合适的值。 要解压缩，有必要根据原始数据的大小选择上下文模型。 描述了检测正确上下文模型的两种方法。 首先，原始数据的大小是压缩数据的一部分。 或者，识别用于压缩原始数据的上下文模型的指示符是压缩数据的一部分。

公开(公告)号：US5778158A

公开(公告)日：1998-07-07

申请号：US610311

申请日：1996-03-04

Applicant: David B. Fujii ,  Robert A. Rust ,  David Hershberger

Inventor： David B. Fujii ,  Robert A. Rust ,  David Hershberger

IPC: H04N1/387 ,  G06T3/40 ,  G06T5/00 ,  G06K15/00

CPC classification number: G06T3/4023

Abstract: A system converts a source image, which may include plural grey level source pixels at a first resolution level, to a destination image at a second resolution level. The system employs a scaling subsystem including a memory which stores at least a portion of a row of source pixels, a scale factor and a relative input index array (RIIA) comprising a single index bit for each column of the destination image. Each index bit enables a grey level source pixel to be identified to be used in scaling of the source image to the second resolution. A scale logic circuit is responsive to each index bit and the source pixels, to associate at least one source pixel with each column of the destination image. The scaling subsystem further includes a control processor which calculates the RIIA based upon the scale factor stored in the memory.

Abstract translation: 系统将源图像（其可以包括处于第一分辨率级别的多个灰度级像素）以第二分辨率级别转换为目的地图像。 该系统采用缩放子系统，其包括存储源像素行的至少一部分的存储器，包括目标图像的每列的单个索引位的比例因子和相对输入索引阵列（RIIA）。 每个索引位使得能够识别用于将源图像缩放到第二分辨率的灰度级源像素。 比例逻辑电路响应于每个索引位和源像素，以将至少一个源像素与目的地图像的每一列相关联。 缩放子系统还包括控制处理器，其基于存储在存储器中的比例因子来计算RIIA。

公开(公告)号：US5771105A

公开(公告)日：1998-06-23

申请号：US606468

申请日：1996-03-04

Applicant: Robert A. Rust ,  David B. Fujii

Inventor： Robert A. Rust ,  David B. Fujii

IPC: H04N1/387 ,  G06T3/40 ,  G06T5/00 ,  H04N1/40 ,  H04N1/405 ,  G06K9/36

CPC classification number: H04N1/4055 ,  G06T3/403 ,  H04N1/40068

Abstract: A system converts a source image of grey level pixel values into a destination image of binary pixel values, the source and destination images having different levels of resolution. The system includes a memory which stores at least a portion of a row of source pixels, a corresponding row of a grey level threshold matrix and a relative input index array (RIIA) which employs a single index bit for each column of the destination image. Index bits are read from the memory and placed in an index bit register, and N source pixel values are written into a source register. A scale logic circuit includes N destination image column outputs and is responsive to each index bit, to output one grey level source pixel on each output. An alignment switch is responsive to a clock input to provide N threshold pixel value outputs that are aligned with corresponding destination image pixels. A comparator compares each source grey level pixel with a corresponding threshold pixel value and assigns a binary value in accordance with the comparison action. A controller initially loads the registers with values from the memory and then synchronously operates the system to output, in parallel, N destination image binary pixel values per clock cycle.

Abstract translation: 系统将灰度级像素值的源图像转换为二进制像素值的目标图像，源和目标图像具有不同的分辨率水平。 该系统包括存储器，其存储源像素行的至少一部分，灰度级阈值矩阵的相应行和相对输入索引阵列（RIIA），其针对目的地图像的每一列采用单个索引位。 索引位从存储器读取并放置在索引位寄存器中，N个源像素值被写入源寄存器。 比例逻辑电路包括N个目的地图像列输出并响应于每个索引位，以在每个输出上输出一个灰度级源像素。 对准开关响应于时钟输入以提供与对应的目的地图像像素对准的N个阈值像素值输出。 比较器将每个源灰度级像素与相应的阈值像素值进行比较，并根据比较动作分配二进制值。 控制器首先从寄存器中加载寄存器，然后同步操作系统，并行输出每个时钟周期的N个目的地图像二进制像素值。

公开(公告)号：US5487138A

公开(公告)日：1996-01-23

申请号：US116181

申请日：1993-09-02

Applicant: Robert A. Rust ,  Wayne A. Overby

Inventor： Robert A. Rust ,  Wayne A. Overby

IPC: B41J2/485 ,  B41J5/30 ,  B41J5/44 ,  G06F3/12 ,  G06K15/12 ,  G06F15/00

CPC classification number: G06K15/12 ,  G06K2215/0014 ,  G06K2215/0065

Abstract: Because laser printers are capable of rendering only a maximum number of characters per unit time, pervious printer would pre-render the entire page prior to print the page. This pre-rendering process greatly increases the memory requirements. To overcome this problem, there is provided a method for reducing memory requirements in a laser printer when printing a page of characters. First, the page is divided into a series of strips. Next, the entire page is scanned strip by strip for any strips that contain an excess number of characters, where the excess number is that number of character that exceeds the maximum number the printer can render in the given time. Assuming a complex strip is found, any common characters in the complex strips are prerendered. If, after pre-rendering the common characters any strip is still complex, then the excess characters are pre-rendered. Finally, each character in a strip is rendered when the printer is ready to print that strip, if any character in the strip was pre-rendered then it is retrieved from memory. Thus, the present invention renders many of the characters while the page is being exposed. Therefore, the printer can start the exposure process sooner and with significantly lower memory requirements.

Abstract translation: 因为激光打印机能够在每单位时间内只能呈现最大数量的字符，所以透明打印机将在打印页面之前预渲染整个页面。 这种预渲染过程大大增加了内存需求。 为了克服这个问题，提供了一种在打印字符页时减少激光打印机中的存储器要求的方法。 首先，页面分为一系列条。 接下来，整个页面按条带逐条扫描，包含超出字符数的条带，其中超出的字符数超过了打印机在给定时间内可以呈现的最大数量。 假设找到一个复杂的条，复合条中的任何常见字符都将被预渲染。 如果在预渲染公用字符之后，任何条纹仍然很复杂，那么多余的字符是预呈现的。 最后，当打印机准备好打印该条时，条带中的每个字符都将被渲染，如果条带中的任何字符都被预先渲染，那么它将从内存中检索。 因此，本发明在页面被曝光时呈现许多字符。 因此，打印机可以更快地开始曝光过程，并且显着降低内存要求。

公开(公告)号：US06687872B2

公开(公告)日：2004-02-03

申请号：US09808910

申请日：2001-03-14

Applicant: Barry J Oldfield ,  Robert A. Rust

Inventor： Barry J Oldfield ,  Robert A. Rust

IPC: G06F1100

CPC classification number: G06F11/1076 ,  G06F2211/1054 ,  G06F2211/1057

Abstract: A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. In one embodiment, parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC). The ASIC includes one or more result buffers for holding intermediate computation results, one or more mathematical operator components configured to receive data segments and coefficients associated with the data segments and operate on them to provide intermediate computation results that can be written to the one or more result buffers, and one or more feedback lines. The feedback lines are coupled between an associated result buffer and an associated mathematical operator component and provide an intermediate computation result to the math operator for use in calculating parity segments.