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    METHOD OF MANUFACTURING ELECTRONIC DEVICES AND CORRESPONDING ELECTRONIC DEVICE
    1.
    发明申请
    METHOD OF MANUFACTURING ELECTRONIC DEVICES AND CORRESPONDING ELECTRONIC DEVICE 有权

    公开(公告)号：US20230110259A1

    公开(公告)日：2023-04-13

    申请号：US18079704

    申请日：2022-12-12

    Applicant: STMicroelectronics (MALTA) Ltd ,  STMicroelectronics S.r.l.

    Inventor： Kevin FORMOSA ,  Marco DEL SARTO

    IPC: B81C1/00 ,  B81B7/00

    Abstract: A first electronic component, such as a sensor having opposed first and second surfaces and a first thickness, is arranged on a support member with the second surface facing towards the support member. A second electronic component, such as an integrated circuit mounted on a substrate and having a second thickness less than the first thickness, is arranged on the support member with a substrate surface opposed the second electronic component facing towards the support member. A package molding material is molded onto the support member to encapsulate the second electronic component while leaving exposed the first surface of the first electronic component. The support member is then removed to expose the second surface of the first electronic component and the substrate surface of the substrate.

    INTEGRATED CIRCUIT PACKAGE WITH WARPAGE CONTROL USING CAVITY FORMED IN LAMINATED SUBSTRATE BELOW THE INTEGRATED CIRCUIT DIE
    2.
    发明申请
    INTEGRATED CIRCUIT PACKAGE WITH WARPAGE CONTROL USING CAVITY FORMED IN LAMINATED SUBSTRATE BELOW THE INTEGRATED CIRCUIT DIE 有权

    公开(公告)号：US20230046645A1

    公开(公告)日：2023-02-16

    申请号：US17870235

    申请日：2022-07-21

    Applicant: STMicroelectronics (Malta) Ltd.

    Inventor： Roseanne DUCA

    IPC: H01L23/498 ,  H01L23/00 ,  B81B7/00

    Abstract: A support substrate includes an insulating core layer, an electrically conductive layer over the insulating core layer and a solder mask layer over the electrically conductive layer. A back side of an integrated circuit chip is mounted to an upper surface of the support substrate at a die attach location. The upper surface of the support substrate includes a cavity located within the die attach location, where the cavity extends under the back side of the integrated circuit chip. The cavity is defined by an area where the solder mask layer and at least a portion of the electrically conductive layer have been removed. Bonding wires connect connection pads on a front side of the integrated circuit chip to connection pad on the upper surface of the support substrate.

    SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD 有权

    公开(公告)号：US20230005755A1

    公开(公告)日：2023-01-05

    申请号：US17942843

    申请日：2022-09-12

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (MALTA) Ltd

    Inventor： Roseanne DUCA ,  Dario PACI ,  Pierpaolo RECANATINI

    IPC: H01L21/324 ,  H01L23/16 ,  H01L23/31

    Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.

    WAFER LEVEL PACKAGE FOR A MEMS SENSOR DEVICE AND CORRESPONDING MANUFACTURING PROCESS
    9.
    发明申请
    WAFER LEVEL PACKAGE FOR A MEMS SENSOR DEVICE AND CORRESPONDING MANUFACTURING PROCESS 有权
    MEMS传感器装置的水平包装和相应的制造工艺

    公开(公告)号：US20160185593A1

    公开(公告)日：2016-06-30

    申请号：US14860157

    申请日：2015-09-21

    Applicant: STMICROELECTRONICS (MALTA) LTD

    Inventor： Conrad CACHIA ,  David Oscar VELLA ,  Damian AGIUS ,  Maria SPITERI

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/007 ,  B81B2207/098 ,  B81C1/00301 ,  B81C2203/0154 ,  H01L23/3121 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2924/00012 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

    Abstract: A MEMS device having a wafer-level package, is provided with: a stack of a first die and a second die, defining at least a first internal surface internal to the package and carrying at least an electrical contact pad, and at least a first external surface external to the package and defining a first outer face of the package; and a mold compound, at least in part coating the stack of the first and second dies and having a front surface defining at least part of a second outer face of the package, opposite to the first outer face. The MEMS device is further provided with: at least a vertical connection structure extending from the contact pad at the first internal surface towards the front surface of the mold compound; and at least an external connection element, electrically coupled to the vertical connection structure and exposed to the outside of the package, at the second outer face thereof.

    Abstract translation: 具有晶片级封装的MEMS器件提供有：第一管芯和第二管芯的堆叠，其限定至少一个封装内部的第一内表面，并且至少承载一个电接触焊盘，以及至少第一管 外部表面，并且限定包装的第一外表面; 以及模具化合物，至少部分地涂覆第一和第二模具的堆叠并且具有限定与第一外表面相对的包装的第二外表面的至少一部分的前表面。 所述MEMS器件进一步具有：从所述接触焊盘在所述第一内表面向模具化合物的前表面延伸的至少垂直连接结构; 以及至少一个外部连接元件，其在垂直连接结构处电耦合并暴露于封装的外部。

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