公开(公告)号：US08384452B1

公开(公告)日：2013-02-26

申请号：US13231798

申请日：2011-09-13

Applicant: Kevin Parker ,  Malcolm Stevens ,  Stephane Dallaire ,  Shawn Scouten ,  Jeff P. Kirsten

Inventor： Kevin Parker ,  Malcolm Stevens ,  Stephane Dallaire ,  Shawn Scouten ,  Jeff P. Kirsten

IPC: H03L7/06

CPC classification number: H03L7/23 ,  H03L7/07 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/18 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

Abstract: A phase difference between a reference clock signal and a feedback signal is digitally detected. A resultant phase detection signal is digitally filtered, and a PLL (Phase Locked Loop) output signal is synthesized in a fractional synthesizer under control of the digitally filtered phase detection signal. A feedback path, which could include an integer divider and/or a fractional N divider, provides the feedback signal based on the PLL output signal. The combination of a wide bandwidth fractional synthesizer and a low bandwidth digital PLL provides for a low bandwidth jitter filtering function with a wide bandwidth PLL to suppress VCO (Voltage Controlled Oscillator) noise and crosstalk.

Abstract translation: 数字检测参考时钟信号和反馈信号之间的相位差。 合成相位检测信号被数字滤波，并且在数字滤波相位检测信号的控制下，在分数合成器中合成PLL（锁相环）输出信号。 可以包括整数分频器和/或分数N分频器的反馈路径基于PLL输出信号提供反馈信号。 宽带分数合成器和低带宽数字PLL的组合提供了具有宽带宽PLL的低带宽抖动滤波功能，以抑制VCO（压控振荡器）噪声和串扰。

公开(公告)号：US20080094107A1

公开(公告)日：2008-04-24

申请号：US11583785

申请日：2006-10-20

Applicant: Stephane Dallaire ,  Brian Glenn Wall ,  Shawn Lawrence Scouten ,  Colin Harvey Cramm ,  Kenji Suzuki ,  Stephen Alie ,  Andrew Deczky

Inventor： Stephane Dallaire ,  Brian Glenn Wall ,  Shawn Lawrence Scouten ,  Colin Harvey Cramm ,  Kenji Suzuki ,  Stephen Alie ,  Andrew Deczky

IPC: H03K5/22

CPC classification number: H03K5/2481 ,  H04L25/0292 ,  H04L25/03019 ,  H04L2025/03617

Abstract: Signal magnitude comparison apparatus and methods are disclosed. A first input circuit receives a differential input signal and provides a first output signal based on a magnitude of the differential input signal. A second input circuit is operatively coupled to the first input circuit and is operable to receive a second input signal, which may also be a differential signal, and to provide a second output signal based on a magnitude of the second input signal. The operative coupling between the first and second input circuits results in the first output signal and the second output signal forming a differential output signal that is indicative of a difference between the magnitude of the first differential input signal and the magnitude of the second input signal.

Abstract translation: 公开了信号幅度比较装置和方法。 第一输入电路接收差分输入信号，并且基于差分输入信号的幅度提供第一输出信号。 第二输入电路可操作地耦合到第一输入电路并且可操作以接收第二输入信号，其也可以是差分信号，并且基于第二输入信号的幅度来提供第二输出信号。 第一和第二输入电路之间的操作耦合导致第一输出信号和第二输出信号形成差分输出信号，该差分输出信号指示第一差分输入信号的幅度与第二输入信号的大小之间的差异。

公开(公告)号：US09559877B1

公开(公告)日：2017-01-31

申请号：US14921251

申请日：2015-10-23

Applicant: Stephane Dallaire ,  Benjamin Smith

Inventor： Stephane Dallaire ,  Benjamin Smith

IPC: H03H7/40 ,  H04L25/03 ,  H04L7/033 ,  H04L7/00 ,  H04L27/06

CPC classification number: H04L25/03006 ,  H04L7/027 ,  H04L25/03057 ,  H04L25/03885

Abstract: Clock timing skew may occur during operation of a time-interleaved receiver. It would be beneficial to try to determine if there is timing skew, and if there is, then address it, such as by reducing or eliminating some or all of the timing skew. Embodiments are described herein that may achieve this. In one embodiment, a method includes generating at least two clocks having the same frequency but a different phase. Intersymbol interference (ISI) values are then determined, one for each of the clocks, by: for each clock, sampling a signal using the clock and determining a value representing ISI based on the sampled signal. A clock phase of at least one of the clocks is adjusted in response to at least one of the ISI values being different from a reference ISI value.

Abstract translation: 在时间交织的接收机的操作期间可能发生时钟定时偏移。 尝试确定是否存在定时偏移将是有益的，并且如果存在，则将其解决，例如通过减少或消除部分或全部时序偏差。 这里描述的实施例可以实现这一点。 在一个实施例中，一种方法包括产生具有相同频率但不同相位的至少两个时钟。 然后通过以下方式确定每个时钟一个的符号间干扰（ISI）值：对于每个时钟，使用时钟对信号进行采样，并且基于采样信号确定表示ISI的值。 响应于至少一个ISI值与参考ISI值不同，调整至少一个时钟的时钟相位。

公开(公告)号：US08184686B2

公开(公告)日：2012-05-22

申请号：US11651632

申请日：2007-01-10

Applicant: Brian Wall ,  Stephane Dallaire ,  Stephen Alie ,  Kenji Suzuki

Inventor： Brian Wall ,  Stephane Dallaire ,  Stephen Alie ,  Kenji Suzuki

IPC: H03H7/30

CPC classification number: H04L25/03057 ,  H03L7/08 ,  H04L7/0087 ,  H04L7/033 ,  H04L2025/03503

Abstract: According to a first aspect, there is provided a circuit for recovering data received over a communication channel. The circuit includes an adaptive equalizer operable to remove ISI (intersymbol interference) from a received signal and a timing recovery circuit operable to sample recovered data. The timing recovery circuit includes a detector based on a Hogge Phase detector. According to another aspect, there is provided a module in which the circuit may be implemented. According to another aspect, there is provided a method for recovering data received over a communication channel. The method involves removing ISI from a received signal using an adaptive equalizer, and sampling recovered data using a detector based on a Hogge phase detector. According to another aspect, the timing recovery circuit includes a plurality of phase detectors, each one being operable to sample recovered data. A selector is provided for selecting which sampled recovered data is to be output.

Abstract translation: 根据第一方面，提供一种用于恢复通过通信信道接收的数据的电路。 该电路包括可操作以从接收信号中去除ISI（符号间干扰）的自适应均衡器和可操作以对恢复数据进行采样的定时恢复电路。 定时恢复电路包括基于霍格相位检测器的检测器。 根据另一方面，提供了一种可以实现电路的模块。 根据另一方面，提供了一种用于恢复在通信信道上接收的数据的方法。 该方法包括使用自适应均衡器从接收到的信号中去除ISI，并且使用基于霍格相位检测器的检测器对恢复的数据进行采样。 根据另一方面，定时恢复电路包括多个相位检测器，每个相位检测器可操作以对恢复的数据进行采样。 提供选择器用于选择要输出哪些采样的恢复数据。

公开(公告)号：US20080165841A1

公开(公告)日：2008-07-10

申请号：US11651632

申请日：2007-01-10

Applicant: Brian Wall ,  Stephane Dallaire ,  Stephen Alie ,  Kenji Suzuki

Inventor： Brian Wall ,  Stephane Dallaire ,  Stephen Alie ,  Kenji Suzuki

IPC: H04L25/08

CPC classification number: H04L25/03057 ,  H03L7/08 ,  H04L7/0087 ,  H04L7/033 ,  H04L2025/03503

Abstract: According to a first aspect, there is provided a circuit for recovering data received over a communication channel. The circuit includes an adaptive equalizer operable to remove ISI (intersymbol interference) from a received signal and a timing recovery circuit operable to sample recovered data. The timing recovery circuit includes a detector based on a Hogge Phase detector. According to another aspect, there is provided a module in which the circuit may be implemented. According to another aspect, there is provided a method for recovering data received over a communication channel. The method involves removing ISI from a received signal using an adaptive equalizer, and sampling recovered data using a detector based on a Hogge phase detector. According to another aspect, the timing recovery circuit includes a plurality of phase detectors, each one being operable to sample recovered data. A selector is provided for selecting which sampled recovered data is to be output.

Abstract translation: 根据第一方面，提供一种用于恢复通过通信信道接收的数据的电路。 该电路包括可操作以从接收信号中去除ISI（符号间干扰）的自适应均衡器和可操作以对恢复数据进行采样的定时恢复电路。 定时恢复电路包括基于霍格相位检测器的检测器。 根据另一方面，提供了一种可以实现电路的模块。 根据另一方面，提供了一种用于恢复在通信信道上接收的数据的方法。 该方法包括使用自适应均衡器从接收到的信号中去除ISI，并且使用基于霍格相位检测器的检测器对恢复的数据进行采样。 根据另一方面，定时恢复电路包括多个相位检测器，每个相位检测器可操作以对恢复的数据进行采样。 提供选择器用于选择要输出哪些采样的恢复数据。

公开(公告)号：US20170118046A1

公开(公告)日：2017-04-27

申请号：US15372051

申请日：2016-12-07

Applicant: STEPHANE DALLAIRE ,  BENJAMIN SMITH

Inventor： STEPHANE DALLAIRE ,  BENJAMIN SMITH

IPC: H04L25/03 ,  H04L7/027

CPC classification number: H04L25/03006 ,  H04L7/027 ,  H04L25/03057 ,  H04L25/03885

Abstract: Clock timing skew may occur during operation of a time-interleaved receiver. It would be beneficial to try to determine if there is timing skew, and if there is, then address it, such as by reducing or eliminating some or all of the timing skew. Embodiments are described herein that may achieve this. In one embodiment, a method includes generating at least two clocks having the same frequency but a different phase. Intersymbol interference (ISI) values are then determined, one for each of the clocks, by: for each clock, sampling a signal using the clock and determining a value representing ISI based on the sampled signal. A clock phase of at least one of the clocks is adjusted in response to at least one of the ISI values being different from a reference ISI value.