Patent search ap:"Todd B Myers" Page 1

1.

发明申请
Passive placement in wire-bonded microelectronics 审中-公开
Title translation: 无铅放置线焊微电子学

公开(公告)号：US20080093723A1

公开(公告)日：2008-04-24

申请号：US11584383

申请日：2006-10-19

Applicant: Todd B. Myers , Chunho Kim , Seung Ae Lee , Suresh B. Yeruva

Inventor： Todd B. Myers , Chunho Kim , Seung Ae Lee , Suresh B. Yeruva

IPC: H01L23/02 , H01L21/00

CPC classification number: H01L25/0657 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06575 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19103 , H01L2924/19105 , H01L2924/00 , H01L2924/00012

Abstract: A microelectronic assembly includes a first microelectronic device electrically coupled with a second microelectronic device via wire bond attachment, the first microelectronic device being structurally coupled with the second microelectronic device via a polymer adhesive, and one or more passive(s) coupled with the first microelectronic device wherein at least one or more passive(s) are enclosed in the polymer adhesive between the first and second microelectronic devices.

Abstract translation: 微电子组件包括通过引线键合附接与第二微电子器件电耦合的第一微电子器件，第一微电子器件通过聚合物粘合剂在结构上与第二微电子器件耦合，以及与第一微电子器件耦合的一个或多个无源器件其中在第一和第二微电子器件之间的聚合物粘合剂中封入至少一个或多个无源器件。

2.

发明授权
Method of embedding passive component within via 有权
Title translation: 无源元件嵌入通孔的方法

公开(公告)号：US07952202B2

公开(公告)日：2011-05-31

申请号：US11847985

申请日：2007-08-30

Applicant: Todd B Myers , Nicholas R. Watts , Eric C Palmer , Jui Min Lim

Inventor： Todd B Myers , Nicholas R. Watts , Eric C Palmer , Jui Min Lim

IPC: H01L23/48 , H01L23/52

CPC classification number: H01L21/76897 , H01L21/486 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/64 , H01L23/66 , H01L2223/6616 , H01L2924/0002 , H01L2924/15311 , H01L2924/1902 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/06 , H05K3/4053 , H05K3/421 , H05K2201/086 , H05K2201/09509 , H05K2201/09563 , H05K2201/0959 , H05K2201/09645 , H05K2201/09663 , H05K2201/09763 , H05K2201/09809 , H05K2201/09827 , H05K2201/09981 , Y10S257/916 , Y10T29/435 , Y10T29/49002 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49147 , Y10T29/49165 , H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。还公开了一种在其中具有一对导电路径的通孔。

3.

发明授权
Via including multiple electrical paths 有权
Title translation: 通过包括多个电路径

公开(公告)号：US07183653B2

公开(公告)日：2007-02-27

申请号：US10740957

申请日：2003-12-17

Applicant: Todd B Myers , Nicholas R. Watts , Eric C Palmer , Renee M Defeo , Jui Min Lim

Inventor： Todd B Myers , Nicholas R. Watts , Eric C Palmer , Renee M Defeo , Jui Min Lim

IPC: H01L23/48 , H01L23/52

CPC classification number: H01L23/49827 , H01L2924/0002 , H05K1/115 , H05K3/064 , H05K3/403 , H05K3/4644 , H05K2201/09645 , H05K2201/09827 , H01L2924/00

Abstract: A system includes a device having at least one integrated circuit. The integrated circuit further includes a first layer of conductive material, a second layer of conductive material, and a via having multiple electrical paths for interconnecting the first layer of conductive material and the second layer of conductive material. A method for forming a via includes drilling an opening to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.

Abstract translation: 一种系统包括具有至少一个集成电路的装置。集成电路还包括第一导电材料层，第二导电材料层，以及具有用于互连导电材料的第一层和第二导电材料层的多条电路的通路。用于形成通孔的方法包括将开口钻出一定深度以露出第一垫和第二垫，用导电材料衬套开口，并将开口中的衬里的第一部分与衬里的第二部分绝缘所述开口形成接触所述第一焊盘的第一电路径和与所述第二焊盘接触的第二电路径。

4.

发明申请
PASSIVE WITHIN VIA 审中-公开
Title translation: 被偷走在威盛

公开(公告)号：US20130249112A1

公开(公告)日：2013-09-26

申请号：US13897202

申请日：2013-05-17

Applicant: Todd B. Myers , Nicolas R. Watts , Eric C. Palmer , Jui Min Lim

Inventor： Todd B. Myers , Nicolas R. Watts , Eric C. Palmer , Jui Min Lim

IPC: H01L21/768 , H01L23/48

CPC classification number: H01L21/76897 , H01L21/486 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/64 , H01L23/66 , H01L2223/6616 , H01L2924/0002 , H01L2924/15311 , H01L2924/1902 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/06 , H05K3/4053 , H05K3/421 , H05K2201/086 , H05K2201/09509 , H05K2201/09563 , H05K2201/0959 , H05K2201/09645 , H05K2201/09663 , H05K2201/09763 , H05K2201/09809 , H05K2201/09827 , H05K2201/09981 , Y10S257/916 , Y10T29/435 , Y10T29/49002 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49147 , Y10T29/49165 , H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。还公开了一种在其中具有一对导电路径的通孔。

5.

发明授权
Method of embedding passive component within via 有权
Title translation: 无源元件嵌入通孔的方法

公开(公告)号：US08487446B2

公开(公告)日：2013-07-16

申请号：US13095317

申请日：2011-04-27

Applicant: Todd B Myers , Nicolas R Watts , Eric C Palmer , Jui Min Lim

Inventor： Todd B Myers , Nicolas R Watts , Eric C Palmer , Jui Min Lim

IPC: H01L23/48 , H01L23/52

CPC classification number: H01L21/76897 , H01L21/486 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/64 , H01L23/66 , H01L2223/6616 , H01L2924/0002 , H01L2924/15311 , H01L2924/1902 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/06 , H05K3/4053 , H05K3/421 , H05K2201/086 , H05K2201/09509 , H05K2201/09563 , H05K2201/0959 , H05K2201/09645 , H05K2201/09663 , H05K2201/09763 , H05K2201/09809 , H05K2201/09827 , H05K2201/09981 , Y10S257/916 , Y10T29/435 , Y10T29/49002 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49147 , Y10T29/49165 , H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。还公开了一种在其中具有一对导电路径的通孔。

6.

发明申请
METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA 有权
Title translation: 嵌入式无源元件的方法

公开(公告)号：US20110198723A1

公开(公告)日：2011-08-18

申请号：US13095317

申请日：2011-04-27

Applicant: Todd B. Myers , Nicholas R. Watts , Eric C. Palmer , Jui Min Lim

Inventor： Todd B. Myers , Nicholas R. Watts , Eric C. Palmer , Jui Min Lim

IPC: H01L29/92

CPC classification number: H01L21/76897 , H01L21/486 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/64 , H01L23/66 , H01L2223/6616 , H01L2924/0002 , H01L2924/15311 , H01L2924/1902 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/06 , H05K3/4053 , H05K3/421 , H05K2201/086 , H05K2201/09509 , H05K2201/09563 , H05K2201/0959 , H05K2201/09645 , H05K2201/09663 , H05K2201/09763 , H05K2201/09809 , H05K2201/09827 , H05K2201/09981 , Y10S257/916 , Y10T29/435 , Y10T29/49002 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49147 , Y10T29/49165 , H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。还公开了一种在其中具有一对导电路径的通孔。

7.

发明授权
Via including multiple electrical paths 有权
Title translation: 通过包括多个电路径

公开(公告)号：US07737025B2

公开(公告)日：2010-06-15

申请号：US11626606

申请日：2007-01-24

Applicant: Todd B Myers , Nicholas R. Watts , Eric C Palmer , Renee M Defeo , Jui Min Lim

Inventor： Todd B Myers , Nicholas R. Watts , Eric C Palmer , Renee M Defeo , Jui Min Lim

IPC: H01L21/00

CPC classification number: H01L23/49827 , H01L2924/0002 , H05K1/115 , H05K3/064 , H05K3/403 , H05K3/4644 , H05K2201/09645 , H05K2201/09827 , H01L2924/00

Abstract: A method for forming an plurality of paths on a substrate includes drilling an opening for a via to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.

Abstract translation: 一种用于在基板上形成多个路径的方法包括：将用于通孔的开口钻出一定深度，以暴露第一垫和第二垫，用导电材料衬套开口，并将开口的第一部分在开口从开口中的衬里的第二部分形成接触第一焊盘的第一电路径和接触第二焊盘的第二电路径。