公开(公告)号：US09410233B2

公开(公告)日：2016-08-09

申请号：US13243944

申请日：2011-09-23

Applicant: Xiaoying Meng ,  Junqing Zhou ,  Haiyang Zhang

Inventor： Xiaoying Meng ,  Junqing Zhou ,  Haiyang Zhang

IPC: H01L29/02 ,  C23C14/00 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/423 ,  C23C14/06

CPC classification number: C23C14/0036 ,  C23C14/0005 ,  C23C14/0641 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32135 ,  H01L21/32137 ,  H01L29/42376

Abstract: A method of manufacturing semiconductor device and a wafer are provided in accordance with embodiments of the present invention, which relates to semiconductor technology. The method includes: providing a substrate, and forming a gate oxide layer and a polysilicon layer on a first surface of the substrate; etching the polysilicon layer by use of a patterned mask so as to form a polysilicon gate with reentrants; depositing a tensile stress film on a second surface of the substrate before etching the polysilicon layer. The tensile stress film can be deposited on the second surface of the substrate for generating the tensile stress for the wafer. Thus, a polysilicon gate with reentrants can be formed in etching process. In this way, semiconductor devices can have smaller gate-source/drain overlap capacitance and better TDDB parameters, and the performance of the devices can be improved.

Abstract translation: 根据涉及半导体技术的本发明的实施例，提供一种制造半导体器件和晶片的方法。 该方法包括：提供衬底，并在衬底的第一表面上形成栅极氧化物层和多晶硅层; 通过使用图案化掩模蚀刻多晶硅层，以形成具有折入物的多晶硅栅极; 在蚀刻多晶硅层之前，在基板的第二表面上沉积拉伸应力膜。 拉伸应力膜可以沉积在基板的第二表面上，以产生晶片的拉伸应力。 因此，可以在蚀刻工艺中形成具有折入物的多晶硅栅极。 以这种方式，半导体器件可以具有更小的栅极/漏极重叠电容和更好的TDDB参数，并且可以提高器件的性能。

公开(公告)号：US20120289017A1

公开(公告)日：2012-11-15

申请号：US13326275

申请日：2011-12-14

Applicant: XIAOYING MENG ,  Junqing Zhou ,  Haiyang Zhang

Inventor： XIAOYING MENG ,  Junqing Zhou ,  Haiyang Zhang

IPC: H01L21/336

CPC classification number: H01L21/31138

Abstract: A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D2 or T2 into the ashing chamber, and ashing the photo resist residue using a plasma that is formed from the gas mixture. The gas mixture can include a deuterium gas or a tritium gas having a volume ratio ranging between about 1% and about 20%. Embodiments can reduce Si recess and the loss of silicon nitride thin film during ashing.

Abstract translation: 一种制造半导体器件的方法包括将半导体衬底放置在灰化室中，所述半导体衬底具有形成在其上的栅极，氮化硅栅极侧壁偏移间隔物或氮化硅栅极侧壁起搏器以及保留在半导体上的光致抗蚀剂残留物 将包括D2或T2的气体混合物引入灰化室，以及使用由气体混合物形成的等离子体使光致抗蚀剂残渣灰化。 气体混合物可以包括体积比在约1％和约20％之间的氘气或氚气体。 实施例可以减少Si凹陷和灰化期间氮化硅薄膜的损失。

公开(公告)号：US08753930B2

公开(公告)日：2014-06-17

申请号：US13326275

申请日：2011-12-14

Applicant: Xiaoying Meng ,  Junqing Zhou ,  Haiyang Zhang

Inventor： Xiaoying Meng ,  Junqing Zhou ,  Haiyang Zhang

IPC: H01L21/302 ,  H01L21/336 ,  H01L21/461

CPC classification number: H01L21/31138

Abstract: A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D2 or T2 into the ashing chamber, and ashing the photo resist residue using a plasma that is formed from the gas mixture. The gas mixture can include a deuterium gas or a tritium gas having a volume ratio ranging between about 1% and about 20%. Embodiments can reduce Si recess and the loss of silicon nitride thin film during ashing.

Abstract translation: 一种制造半导体器件的方法包括将半导体衬底放置在灰化室中，所述半导体衬底具有形成在其上的栅极，氮化硅栅极侧壁偏移间隔物或氮化硅栅极侧壁起搏器以及保留在半导体上的光致抗蚀剂残留物 将包括D2或T2的气体混合物引入灰化室，以及使用由气体混合物形成的等离子体使光致抗蚀剂残渣灰化。 气体混合物可以包括体积比在约1％和约20％之间的氘气或氚气体。 实施例可以减少Si凹陷和灰化期间氮化硅薄膜的损失。

公开(公告)号：US20130059438A1

公开(公告)日：2013-03-07

申请号：US13293979

申请日：2011-11-10

Applicant: JUNQING ZHOU ,  XIAOYING MENG ,  HAIYANG ZHANG

Inventor： JUNQING ZHOU ,  XIAOYING MENG ,  HAIYANG ZHANG

IPC: H01L21/306 ,  B44C1/22 ,  B29C59/02

CPC classification number: H01L21/0332 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/165 ,  H01L21/0337 ,  H01L21/0338

Abstract: A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps.

Abstract translation: 在本公开中提供了图案形成方法，掩模图案形成方法和半导体器件的制造方法，其涉及半导体工艺领域。 图案形成方法包括：提供基板; 在基材上形成含有嵌段共聚物的聚合物薄膜; 通过用印模压印聚合物薄膜来形成第一图案; 通过在第一图案中共聚物的定向自组装形成由不同共聚物组分组成的畴; 选择性地除去由共聚物组分组成的畴以形成第二图案。 在本发明的实施例中，可以通过组合压印和DSA处理而不曝光来获得更细的间距图案，与现有技术的方法相比，其简单性优点。 此外，在印记中使用的邮票可以具有相对更大的间距，便于和简化邮票的制造和对准。

公开(公告)号：US20120273923A1

公开(公告)日：2012-11-01

申请号：US13243944

申请日：2011-09-23

Applicant: Xiaoying Meng ,  Junqing Zhou ,  Haiyang Zhang

Inventor： Xiaoying Meng ,  Junqing Zhou ,  Haiyang Zhang

IPC: H01L29/02 ,  H01L21/308

CPC classification number: C23C14/0036 ,  C23C14/0005 ,  C23C14/0641 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32135 ,  H01L21/32137 ,  H01L29/42376

Abstract: A method of manufacturing semiconductor device and a wafer are provided in accordance with embodiments of the present invention, which relates to semiconductor technology. The method includes: providing a substrate, and forming a gate oxide layer and a polysilicon layer on a first surface of the substrate; etching the polysilicon layer by use of a patterned mask so as to form a polysilicon gate with reentrants; depositing a tensile stress film on a second surface of the substrate before etching the polysilicon layer. The tensile stress film can be deposited on the second surface of the substrate for generating the tensile stress for the wafer. Thus, a polysilicon gate with reentrants can be formed in etching process. In this way, semiconductor devices can have smaller gate-source/drain overlap capacitance and better TDDB parameters, and the performance of the devices can be improved.

Abstract translation: 根据涉及半导体技术的本发明的实施例，提供一种制造半导体器件和晶片的方法。 该方法包括：提供衬底，并在衬底的第一表面上形成栅极氧化物层和多晶硅层; 通过使用图案化掩模蚀刻多晶硅层，以形成具有折入物的多晶硅栅极; 在蚀刻多晶硅层之前，在基板的第二表面上沉积拉伸应力膜。 拉伸应力膜可以沉积在基板的第二表面上，以产生晶片的拉伸应力。 因此，可以在蚀刻工艺中形成具有折入物的多晶硅栅极。 以这种方式，半导体器件可以具有更小的栅极/漏极重叠电容和更好的TDDB参数，并且可以提高器件的性能。

公开(公告)号：US08828871B2

公开(公告)日：2014-09-09

申请号：US13293979

申请日：2011-11-10

Applicant: Junqing Zhou ,  Xiaoying Meng ,  Haiyang Zhang

Inventor： Junqing Zhou ,  Xiaoying Meng ,  Haiyang Zhang

IPC: H01L21/306 ,  B44C1/22 ,  B29C59/02

CPC classification number: H01L21/0332 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/165 ,  H01L21/0337 ,  H01L21/0338

Abstract: A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps.

Abstract translation: 在本公开中提供了图案形成方法，掩模图案形成方法和半导体器件的制造方法，其涉及半导体工艺领域。 图案形成方法包括：提供基板; 在基材上形成含有嵌段共聚物的聚合物薄膜; 通过用印模压印聚合物薄膜来形成第一图案; 通过在第一图案中共聚物的定向自组装形成由不同共聚物组分组成的畴; 选择性地除去由共聚物组分组成的畴以形成第二图案。 在本发明的实施例中，可以通过组合压印和DSA处理而不曝光来获得更细的间距图案，与现有技术的方法相比，其简单性优点。 此外，在印记中使用的邮票可以具有相对更大的间距，便于和简化邮票的制造和对准。